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Below rules are for standard cell layout, but I don't know whether they also apply to our custom blocks layout?
1. Height of full custom block should be integer multiples of horizontal routing grid defined in standard cell library.
2. Width of full custom block should be...
In our chip there are some blocks in critical timing path, which are custom designed. Because full chip will go with ASIC flow, so full chip layout will be done with PR. Any one can help provide some guideline for the custom layout of these blocks? To integrate these blocks layout to PR, I need...
below is assumptions:
1) TSMC 90nm GP process
2) die size: ~13mm*13mm
3) Flip-chip (RDL)
4) main clock: 250MHz
5) at least two metal layers used for power plan
Generally for backend design, how big utilization and IR drop(Total die IR drop and Total chip IR drop) are resonable?
op design question
Thanks leo_o2 and DZC! I only have model file, no textbooks. My concern is that if I find vth0, tox,u from the model, are these parameters enough accurate for manual calculation results?
Added after 1 minutes:
I want to know original designer how to figure out these...
now I have P/N mos model(BSIM49), as we know, we need manual calculation to solve 80% op design issue, but how to obtain the basic parameters of P/N mos for manual calculation? such as K',Vt,lamda .etc. Thanks a lot!