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  1. J

    Designing a DDR2 controller: strobe issues

    Oh my goodness! Shame on me :grin: Well, I'll keep looking into JEDEC documents, hopefully I'll find something :???:
  2. J

    Designing a DDR2 controller: strobe issues

    Thank you permute for your answer. I've searched on the network for some document about this IIRC algorithm, but I found nothing. Does anyone have a link or some documentation about it?
  3. J

    Designing a DDR2 controller: strobe issues

    Yes, Xilinx provides an IP core for DDR2 RAMs. And yes, I'm sure I want to make one of my own, or at least try to make one :)
  4. J

    Designing a DDR2 controller: strobe issues

    I'm trying to implement a DDR2 controller on a Spartan3 FPGA. The memory is a single 512Mb chip by Micron (32M x 16, that is the data bus is 16 bits wide), and the following is its datasheet: https://download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf Writing the RAM is quite...
  5. J

    Using both falling and rising edge of clock: timing consequences

    Thank you both for your answers. I don't understand :-( Is this true only in the hardware implementation (so it's a direct cause of the routing delays) or is this true even when simulating? (i.e. is this defined by VHDL?) I wrote a simple chunk of code to do some tests: entity top is port(...
  6. J

    Using both falling and rising edge of clock: timing consequences

    Hi there, I have a project that involves a state machine. Some states require the machine to wait for a certain amount of time. I thought of implementing the delays using some simple counters, so the design would be something like: process(clk) begin if rising_edge(clk) then -- description...
  7. J

    Soft processor: which one should I go for?

    Wow ryanlxb, you implemented an ARM compatible processor on your own? I have to admit it, I'm impressed. Nice job! Anyway I don't think I'll go for it, I need something more largely supported. Well lucbra, I think I'll go for the Mico32: https://en.wikipedia.org/wiki/LatticeMico32 If there...
  8. J

    Soft processor: which one should I go for?

    Hi there, So far I've been working on embedded projects using AT91SAM7 microcontrollers (an ARM7TDMI core plus plenty of peripherals, made by atmel). Now, after messing around a little bit with a Spartan3 FPGA, I'd like to get it to do some real stuff. At first I thought about the Microblaze...
  9. J

    VHDL: Predicting how many bits an expression is made of

    Yea, I sure would better brake it down. Well, to be honest that constant was born as a generic. Not much time after I discovered the compiler does not like generics as arguments for case statements, because they're not locally static. As a consequence I chose to change it for a constant. The...
  10. J

    VHDL: Predicting how many bits an expression is made of

    Thank you vipinlal! That was helpful, just what I was looking for :) Still, I'd like to know what permute was talking about, maybe it's not the right way to accomplish such an operation ?
  11. J

    VHDL: Predicting how many bits an expression is made of

    Tell me more please! By the way the synthesizer just instantiate some adders, multipliers and stuff for that expression (as I expected). What's wrong with it ? :cry:
  12. J

    VHDL: Predicting how many bits an expression is made of

    Hi there, Let's take the following example: rom_addr := std_logic_vector(unsigned(ram_db)*((font_width*font_height)/8) + (unsigned(pix_x) + unsigned(pix_y)*font_width)/8); Where: signal ram_db: std_logic_vector(7 downto 0); constant font_width: integer range integer'right downto 8 := 8...
  13. J

    VHDL: Selecting the LSBs of an array

    Actually it's tmp. Well, I think I'll need to get used to it :)
  14. J

    VHDL: Selecting the LSBs of an array

    Hi there, I have an expression that results in an array of 22 std_logic values. I have to assign this expression to a variable which can only hold 16 elements, and I'd like elements from 0 to 15 of the expression to be assigned to the variable (the LSBs), and the others to be discarded. I'm...
  15. J

    Video RAM: reading and writing?

    Thanks you both for your hints, they're valuable :) permute, the internal buffer idea sounds just good. vipinlal I don't think I got it a 100% straight. For what I understood you're saying to use a dual buffering technique to accomplish concurrent reading and writing. To accomplish this I'd...
  16. J

    Video RAM: reading and writing?

    Yes vipinlal, that's it! But what if someday I'll need more space and decide to switch to an external DDR RAM? Is there any way to obtain the same behavior from such a RAM? Or should I look for some other specific RAM ? Thank you :)
  17. J

    Video RAM: reading and writing?

    Hi there, I'm designing a VGA signal generator. I'm actually stuck into the design of the RAM interface. The RAM should contain the data that has to be put on the screen by the signal generator. The signal generator requires (should it?) a continuous access to the RAM, this because the screen...

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