Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. J

    Designing a DDR2 controller: strobe issues

    I'm trying to implement a DDR2 controller on a Spartan3 FPGA. The memory is a single 512Mb chip by Micron (32M x 16, that is the data bus is 16 bits wide), and the following is its datasheet: https://download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf Writing the RAM is quite...
  2. J

    Using both falling and rising edge of clock: timing consequences

    Hi there, I have a project that involves a state machine. Some states require the machine to wait for a certain amount of time. I thought of implementing the delays using some simple counters, so the design would be something like: process(clk) begin if rising_edge(clk) then -- description...
  3. J

    Soft processor: which one should I go for?

    Hi there, So far I've been working on embedded projects using AT91SAM7 microcontrollers (an ARM7TDMI core plus plenty of peripherals, made by atmel). Now, after messing around a little bit with a Spartan3 FPGA, I'd like to get it to do some real stuff. At first I thought about the Microblaze...
  4. J

    VHDL: Predicting how many bits an expression is made of

    Hi there, Let's take the following example: rom_addr := std_logic_vector(unsigned(ram_db)*((font_width*font_height)/8) + (unsigned(pix_x) + unsigned(pix_y)*font_width)/8); Where: signal ram_db: std_logic_vector(7 downto 0); constant font_width: integer range integer'right downto 8 := 8...
  5. J

    VHDL: Selecting the LSBs of an array

    Hi there, I have an expression that results in an array of 22 std_logic values. I have to assign this expression to a variable which can only hold 16 elements, and I'd like elements from 0 to 15 of the expression to be assigned to the variable (the LSBs), and the others to be discarded. I'm...
  6. J

    Video RAM: reading and writing?

    Hi there, I'm designing a VGA signal generator. I'm actually stuck into the design of the RAM interface. The RAM should contain the data that has to be put on the screen by the signal generator. The signal generator requires (should it?) a continuous access to the RAM, this because the screen...

Part and Inventory Search