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    "Problems encountered during simulation" in cadenc

    problems encountered during simulation Hi, I am running mixed signal simulation in spectre-verilog simulator with digital blocks implemented using verilog and analog blocks with transistors in spectre. I have created a 'config' view to simulate it. When I try to click 'netlist and run'...
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    Running VHDL code integrated with Circuits in Spectre

    Hi, Could anyone please help me running vhdl code integrated with circuits developed using spectre simulator. I need it to run in spectre itself. I ran with veriloga codes. It seems to be working along with designed circuits in spectre but then it is generating errors with vhdl. What should be...
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    Running input.scs file in Cadence

    Could anyone help me in providing the scripting code for running the input.scs file in Cadence, thereby I wanted the netlist to be simulated and run, and also the outputs to be plotted? Thanks, Shankar Thirunakkarasu
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    Ideal Delay block in analogLib (Cadence)

    Hi, When I use an ideal "Delay" block from analogLib in Cadence, with differential signal at its input, it gives the output only at its negative terminal and doesnt provide a differential output. The positive terminal is getting grounded. I would be happy if anybody could share of what is...
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    What does the conversion gain in mixer model of ADS refers to?

    Hi, Could anyone please clear me whether the conversion gain in mixer model of ADS refers to Voltage conversion gain or Power Conversion gain? Thanks, Shankar.T
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    What does the conversion gain in mixer model of ADS refers to?

    Hi, Could anyone please clear me whether the conversion gain in mixer model of ADS refers to Voltage conversion gain or Power Conversion gain? Thanks, Shankar.T
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    Bias Resistor Transistor

    Why is "Bias Resistor Transistor" is used? Please google the word and you can see lot of "Bias resistor transistors" are being sold by different companies? Please tell what is the advantage of this "Bias resistor transistor" holds when compared to the ordinary BJT? In what way is the resistor...
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    How to increase SNDR in FLASH ADC?

    I am doing flash adc and I am getting a signal energy of around 63 dB for some input frequency and for some amplitude but I am getting a distortion of 45 dB and noise of around 40 dB which reduces from SNDR of the ADC. How do I reduce the distortion energy and noise energy? I am using hanning...
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    Basic doubt in analog design in cadence

    When I design an op amp, I notice that if I increase my (W/L) ratio of input transistors to a large extent (kkeping L to some constant value), then vds > vdsat and vgs <vth and the result browser shows that the region of operation is 3. I suppose that region 3 indicates that this is operating in...
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    cascode BJT output impedance

    When I do not connect any load resistance Rd, what is the output impedance of the cascode BJT in terms of gm,ro,r π (pi)?
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    How to increase phase margin of a single stage folded cascode amplifier?

    How to increase phase margin of a single stage folded cascode single ended output amplifier.
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    cadence spectre doubt in finding the regions

    Hi, 1. Is there anyway where I could see the regions in which all the transistors in my design are operating at once. Currently the Results -> Circuit Conditions show me the transistors which are in linear region or breakdown. But it doesnt show other regions. 2. I know region 1 represent...
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    substrate noise analysis on sigma delta adc

    Can anyone guide me on how to do substrate analysis on sigma delta adc. I am not able to find papers which talks about both the substrate noise and sigma delta (both). Can anybody upload those papers which talks about both. I am using spectre and virtuoso for building my sigma delta and I am...
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    help in solving a problem with the AD6644 ADC

    We have a small technical problem with the ADC evaluation board (AD6644) bought from Analog Devices. We would be thankful to you if you can help us in solving this problem. The description of this ADC and the actual problem we faced are given below. ADC Description: This ADC operates with a...
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    What's the meaning of splines?

    Could anyone explain the meaning of splines which is related to signal processing. This is buzz word talked by a number of people nowadays. Or give me a link to read about this.
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    Design considerations for PLL synthesizer

    wat is design consideration of designin a PLL synthesiser.. how diff it is from designing a PLL for tracking
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    Matlab code for generating Rician Random Numbers needed

    generating random numbers in matlab Well I need a matlab code for generating the rician random numbers since matlab does not have the command for generating the rician random numbers. It is needed for me in my project.
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    Altera design contest for India

    I saw a poster regarding ALTERA design contest using a FPGA and NIOS processor for INDIA for which the abstracts had to be submitted before april 15th but I am not able to find this on the net. Could anyone provide more details on it or give me a link to that site for more information.
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    Video interval test signal

    Can anyone suggest me a material to read on the topic Video interval test signal or a link to that. Because it seems to be widely used in Television Engineering.

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