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I read somewhere that it is not advisable to use glue logic in top level module in FPGA design. It's alleged that only entity instantiation is allowed in the top-level module.
Could anyone point out the reason?
BTW: Is 3-state buffer considered as glue logic?
How many of you actually declare a Function or a Procedure in VHDL?
For me, I only use Procedure for simulation.
Is it feasible to use function/procedure for synthesizable designs?
Maybe it's because I haven't done any functional verifcation design?
Thanks Black Jack and Maestor for your suggestions.
Actually due to speed issue, I will use one-hot FSM . So I think 1 large FSM will use the same amount of registers as 3 FSMs. A 30 State FSM is really too big so probably I will adopt the 3 FSMs architecture. :-)
I agree with Black Jack about...
I have one question about FSM implementation using VHDL.
For my project, I can choose to implement a large FSM which contains around 30 states, or I can choose to implement it by 3 smaller FSMs.
Does the synthesizer prefer the latter solution or the large-but-all-in-1 FSM...
so can i say actually they have the same function?
for example: assume the period is 30 ns
the following two constraints actually give the same OFFSET constraint.
OFFSET=IN 20.0 BEFORE "CLK"
OFFSET=IN 10.0 after BEFORE "CLK"
am I right?
I am using a FPGA development board from DINI group.
This board uses a microcontroller to program the FPGA as soon as the PC is powered-on.
You can take a look at the schematic provided in https://www.dinigroup.com/index.php?product=DN3000k10
I have been doing FPGA design for a few months and this question has been rising in my head: Does FPGA designer need to be a "Floorplanning Master"?
Up to now, I have seen a lot of books on FPGA, and most of them focus on VHDL/Verilog Coding. Very few books also talk about...
Well i guess this problem could be solved by floorplanning.
I did a test with FPGA A --- I removed the pin assignment and let ISE assign pins. Guess what is the result? FPGA A passed the timing analysis with Clock set to 144Mhz.
So I think different pin assignment will make the Xilinx...
Re: HDL Synthesis to What
Hi I am also a newbie to FPGA
so far I have been using XST and Synplify as synthesizer.
In Synplify, you can take a look at the "RTL View" which visualize your design. Better try this with a small design.