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  1. S

    No glue logic in top level module?

    Thanks Hamadeh, so is it true that glue logic should be avoided in the top-level entity of fpga design? If it is true, what is the reason?
  2. S

    No glue logic in top level module?

    Hi guys, I read somewhere that it is not advisable to use glue logic in top level module in FPGA design. It's alleged that only entity instantiation is allowed in the top-level module. Could anyone point out the reason? BTW: Is 3-state buffer considered as glue logic? i.e. pci_devsel_n <=...
  3. S

    what is PERL? How do we use it to help FPGA design?

    But it seems that EDA vendors support tcl better. have any one used both tcl & perl for fpga development? any comment?
  4. S

    what is PERL? How do we use it to help FPGA design?

    I am curious about this. Please give me some idea.
  5. S

    Do you guys really use the function & Procedure in VHDL?

    How many of you actually declare a Function or a Procedure in VHDL? For me, I only use Procedure for simulation. Is it feasible to use function/procedure for synthesizable designs? Maybe it's because I haven't done any functional verifcation design?
  6. S

    A large FSM or severl small FSM: which is better?

    Thanks Black Jack and Maestor for your suggestions. Actually due to speed issue, I will use one-hot FSM . So I think 1 large FSM will use the same amount of registers as 3 FSMs. A 30 State FSM is really too big so probably I will adopt the 3 FSMs architecture. :-) I agree with Black Jack about...
  7. S

    A large FSM or severl small FSM: which is better?

    Hi guys, I have one question about FSM implementation using VHDL. For my project, I can choose to implement a large FSM which contains around 30 states, or I can choose to implement it by 3 smaller FSMs. Does the synthesizer prefer the latter solution or the large-but-all-in-1 FSM...
  8. S

    what's the difference between the two xilinx constraints

    so can i say actually they have the same function? for example: assume the period is 30 ns the following two constraints actually give the same OFFSET constraint. OFFSET=IN 20.0 BEFORE "CLK" OFFSET=IN 10.0 after BEFORE "CLK" am I right?
  9. S

    FPGA Design Training Course in Malaysia

    fpga course malaysia you may come to Singapore. Insight has a center here.
  10. S

    what's the difference between the two xilinx constraints

    offset = after valid xilinx "OFFSET IN BEFORE" and "OFFSET IN AFTER" Are they functioning exactly the same?
  11. S

    FPGAs and PCI/PCI-E/PCI-X

    I am using a FPGA development board from DINI group. This board uses a microcontroller to program the FPGA as soon as the PC is powered-on. You can take a look at the schematic provided in https://www.dinigroup.com/index.php?product=DN3000k10
  12. S

    Information about Xilinx ISE 6.3 !

    X1L1NX ISE 6.3 is out just read the "Xilinx 6.3i what's new" The largest improvement: 6.3i supports Virtex4 also, PACE is enhanced.
  13. S

    why TI=1 before printf()?

    I met the same problem before. Tom324 gave the right answer.
  14. S

    Book for C and 8051, which is better?

    Embedded C is good
  15. S

    Does FPGA designer need to be a "Floorplanning Master&q

    Hi guys, I have been doing FPGA design for a few months and this question has been rising in my head: Does FPGA designer need to be a "Floorplanning Master"? Up to now, I have seen a lot of books on FPGA, and most of them focus on VHDL/Verilog Coding. Very few books also talk about...
  16. S

    Hello ,I'm newbie ,I ask for VHDL for beginer

    aldec's interactive Vhdl tutorial is quite good. I also started from that.
  17. S

    CPLD input frequency upper limit

    The max input frequency is determined by a few things, such as the combinational logic delay(level of logic), the chip itself (speed grade)., etc.
  18. S

    generic vs constant in VHDL?

    vhdl constant Oops Didn't know there are so many shortcomings about generics. Thanks delay for your information
  19. S

    The Effect of Pin Assginment to Timing Closure

    Well i guess this problem could be solved by floorplanning. I did a test with FPGA A --- I removed the pin assignment and let ISE assign pins. Guess what is the result? FPGA A passed the timing analysis with Clock set to 144Mhz. So I think different pin assignment will make the Xilinx...
  20. S

    How HDL style converts to particular RTL synthesized circuit

    Re: HDL Synthesis to What Hi I am also a newbie to FPGA so far I have been using XST and Synplify as synthesizer. In Synplify, you can take a look at the "RTL View" which visualize your design. Better try this with a small design.

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