Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I read somewhere that it is not advisable to use glue logic in top level module in FPGA design. It's alleged that only entity instantiation is allowed in the top-level module.
Could anyone point out the reason?
BTW: Is 3-state buffer considered as glue logic?
How many of you actually declare a Function or a Procedure in VHDL?
For me, I only use Procedure for simulation.
Is it feasible to use function/procedure for synthesizable designs?
Maybe it's because I haven't done any functional verifcation design?
I have one question about FSM implementation using VHDL.
For my project, I can choose to implement a large FSM which contains around 30 states, or I can choose to implement it by 3 smaller FSMs.
Does the synthesizer prefer the latter solution or the large-but-all-in-1 FSM...
I have been doing FPGA design for a few months and this question has been rising in my head: Does FPGA designer need to be a "Floorplanning Master"?
Up to now, I have seen a lot of books on FPGA, and most of them focus on VHDL/Verilog Coding. Very few books also talk about...
Currently I am doing with a project which uses 5 Virtex 2 FPGAs(A,B,C,D,E). FPGA E gets data from a PC through the PCI-bus and distributes the data equally to the 5 FPGAs. In each FPGA there are 10 processing units for the incoming data.
Since the 5 FPGAs are carrying out the same...