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  1. S

    No glue logic in top level module?

    Hi guys, I read somewhere that it is not advisable to use glue logic in top level module in FPGA design. It's alleged that only entity instantiation is allowed in the top-level module. Could anyone point out the reason? BTW: Is 3-state buffer considered as glue logic? i.e. pci_devsel_n <=...
  2. S

    what is PERL? How do we use it to help FPGA design?

    I am curious about this. Please give me some idea.
  3. S

    Do you guys really use the function & Procedure in VHDL?

    How many of you actually declare a Function or a Procedure in VHDL? For me, I only use Procedure for simulation. Is it feasible to use function/procedure for synthesizable designs? Maybe it's because I haven't done any functional verifcation design?
  4. S

    A large FSM or severl small FSM: which is better?

    Hi guys, I have one question about FSM implementation using VHDL. For my project, I can choose to implement a large FSM which contains around 30 states, or I can choose to implement it by 3 smaller FSMs. Does the synthesizer prefer the latter solution or the large-but-all-in-1 FSM...
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    what's the difference between the two xilinx constraints

    offset = after valid xilinx "OFFSET IN BEFORE" and "OFFSET IN AFTER" Are they functioning exactly the same?
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    Does FPGA designer need to be a "Floorplanning Master&q

    Hi guys, I have been doing FPGA design for a few months and this question has been rising in my head: Does FPGA designer need to be a "Floorplanning Master"? Up to now, I have seen a lot of books on FPGA, and most of them focus on VHDL/Verilog Coding. Very few books also talk about...
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    The Effect of Pin Assginment to Timing Closure

    Hi All, Currently I am doing with a project which uses 5 Virtex 2 FPGAs(A,B,C,D,E). FPGA E gets data from a PC through the PCI-bus and distributes the data equally to the 5 FPGAs. In each FPGA there are 10 processing units for the incoming data. Since the 5 FPGAs are carrying out the same...

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