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  1. G

    measured power twice the simulation result

    Sure it is. I have no idea what could the reason be. I have a chance to put a test structure on a test chip, so I have to think what structure is appropriate.
  2. G

    measured power twice the simulation result

    I used a high voltage technology for my chip and violated some latch-up design rules. The measured power consumption is around 50 mA which is twice the simulation result. What could be the potential reasons for that? ( my chip is pretty big and complex, so if latch-up happens, it should burn...
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    What if the input of a comparator is the same? What is the phenomena called?

    What if the input of a comparator is the same? The comparator won't make a decision. What is the phenomena called?
  4. G

    what are the specifications of different ADCs used in various applications

    I know ADC are used in audio/video/data acquisition/cellphone/HD TV ... but what are the specifications of different applications like sampling rate and resolution? and how are they used?
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    how to turn on mismatchflag=1 in Cadence with TSMC

    I find the following from design kits doc, however I do not under what does it mean. Marco MOS device usage: 3) MOS with mismatch effect: Please enable the item "With Mismatch Effect" in CDF form of macro MOS devices. It will generate the parameter "mismatchflag=1" in the...
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    how to turn on mismatchflag=1 in Cadence with TSMC

    I tried that and there was no mismatch. That's why I wonder if there is an option to turn on the mismatch in the design kits. I'm using tsmc90nm.
  7. G

    how to turn on mismatchflag=1 in Cadence with TSMC

    From TSMC manual, I find this "The designers will need to turn off (mismatchflag=0) or turn on (mismatchflag=1) in the macro model for nominal or Monte-Carlo analysis". Any idea, how can I turn it on?
  8. G

    What is gm called in tsmc technology?

    Thanks a lot. I was looking for it with the option Print Model Parameters.
  9. G

    What is gm called in tsmc technology?

    Usually you can see the gm of a transistor in ADE when you ran a op analysis. But in the tsmc technology, I can not find it. I am wondering if it is called something else.
  10. G

    ADC voltage reference

    I've seen ADC with on-chip voltage reference. Does an ADC usually have an on-chip reference? The problem is that I am designing an ADC and I need two voltage references (Ref and Ref/16). For writing a paper, I can leave it alone. But for real design, should I worry about the Ref/16 reference...
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    What's the typical value of a comparator input offset?

    This is my dynamic comparator. I ran the Menta Carlo simulation with process and mismatch. The offset is around 1~2mV. So it is not so bad if my vlsb=1mV, is that right? Need for auto-zero?
  12. G

    What's the typical value of a comparator input offset?

    I'm designing a comparator for my 10-bit SAR ADC. Just wondering what's the typical value of the comparator's input offset with careful layout. For 10-bit ADC, do I need to do offset cancellation? I have done a simple dynamic comparator and the post-layout simulation result shows about 1mV...
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    How to use diode to solve antenna violation?

    I have two antenna violation in my layout. Long metal is connected to pmos gate. I plan to use reverse biased diode to solve the problem. how should I connect the other terminal of the diode? If I use N+/pwell diode, should the other end connect to ground ?
  14. G

    assura lvs error with tsmc autofilling tool (no error when dummy metal not merged)

    I am using tsmc90nm. I use autofilling tool provided by tsmc to do filling. When I didn't merge the dummy metal created by that tool, my lvs was correct. But when I merged it, mimcaps and several pins were not correctly bonded. Any idea why? ( My lvs with the merged dummy metal used to be...
  15. G

    assura qrc setting : use field solver or not

    i am using tsmc90nm technology. my design is sensitive to parasitic capcitance, so when i do layout extraction, should i use the assura field solver or not? (rcxfs.dat is provided in the design kit.)
  16. G

    [SOLVED] assura qrc setting : use field solver or not

    i am using tsmc90nm technology. my design is sensitive to parasitic capcitance, so when i do layout extraction, should i use the assura field solver or not?
  17. G

    what is the difference between filling dummy metal and real metal?

    thanks very much for your answering. same as I thought.
  18. G

    what is the difference between filling dummy metal and real metal?

    I am doing metal filing for a comparator. Just wonder what is the difference between dummy metal and real metal. 1) Will all the dymmy metal be fabricated? or it is optional for the foundry. (I want the layout be symmetrical. so if it is optional, I would prefer real metal insted of dummy one)...
  19. G

    drc error :enclosure of chipedge

    Got it. Thanks very much ---------- Post added at 03:49 ---------- Previous post was at 03:48 ----------
  20. G

    drc error :enclosure of chipedge

    I am using tsmc90nm technology. I use calibre to do the DRC. There are errors like xx enclose from the chipedge < xx. I think it is because of the chipedge defined. How should I define the chipedge? or how should I define the area for DRC in calibre? someone tells me i can define the area for...

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