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I received multiple SDF files for the same module. The sdf files are for
-shift mode during dft
-capture mode during dft
-mbist and bsd
Each of those sdf above contains min,typ,max, as usual. My question, during simulation,
-do I read all those sdf, or i just need to read...
Currently I'm doing verification for rtl versus netlist.
The netlist haven't been modified. It comes right after
being sythesized by Synopsys Design Compiler.
The main question in my mind is, why I need to verify the netlist. Is it
means that the tools cannot be trusted? In other...
I have two questions regarding above.
1) Can I insert spare cells using Synopsys design compiler?
2) What are things that need to be considered if I want to do
compilation for design that have spare cells. What I mean
is do I have to do set dont touch for the...
synopsys netlist + solvnet
How do I remove assign statement in a synthesized netlist?
I read somewhere on the net, this assign statement exists
1) Input connected directly to output port
2) There is tristate cell
I'm more concern on how to solve the (1) because in my design,
tx/rx antenna 315 mhz
I need advices from everybody on how to design a microstrip antenna (on pcb)
for 315mhz. For Tx, it's a loop antenna, and rx, it's a monopople PCB trace antenna.
Also, one more thing, I just need to do transmission for a short distance
only about 3 or 4 meters...