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spectreVerilog has error below:
Error! Line is too long - being truncated [Verilog-LTLT]
Error! sysntax error [Verilog]
How can I fix the above errror?
Anyone can help?? Pls.
I need it in my program.
But anyway, I have found the solution.
Just convert sch.oa or symbol.oa using linux shell script command like "strings", and all the information is there.
Thank you for your reply.c", )