Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. V

    What's effect on max_fanout and max capacitance violation?

    max capacitance What's effect on max_fanout and max capacitance violation? Currently,my design has no timing violation and max transition violation,but there are still 2 violations:max fanout and max capacitance violations on the system main clock, which I have set "dont_touch_network"...

Part and Inventory Search

Top