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Type: Posts; User: alam.tauqueer

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  1. Closed: what is user-defined attributes in SV??

    Hi,

    Can anyone tell me about the user-defined attributes in system verilog with example?

    Regards.
    tauqueer
  2. Closed: What is the $clog2 built-in function do in systemverilog???

    Hi All,

    Can anyone tell me what is the meaning of $clog2 in SV??

    Please tell me the usage also and where I can get the information on it??

    I have a expression like

    localparam param1 =...
  3. Closed: Width of unsized based number like 'b1, 'b0, and 'b10

    Hi,

    Can anyone tell me what would be the width of LHS and RHS

    out[3:0] = 'b1;
    out[3:0] = 'b0;
    out[3:0] = 'b10;

    should we take RHS width as 1 ??
  4. Closed: magma.command

    Hi ,

    Is it possible to check multiple drivers in magma through some switch ??

    I have a design where a signal is multiply driven and I want to detect it through magma. can we get this...
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    Closed: self determined expression

    can anyone explain what is self determined expression??
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    Closed: pad cell structure

    Hi,

    What is the strcuture of a pad cells??

    can any one tell me where I can get it??

    regards,
    tauqueer
  7. Closed: Can verilog file (.v) used as library??

    I am using magma blast.

    Please tell me how the tool will treat these two library file one .v and other is .lib ??
    Is there any difference in the netlist generated by synthesis tools??
  8. Closed: Can verilog file (.v) used as library??

    Hi ,

    Can anyone tell me if a verilog file can be used as a library file??

    Below given module is a library?? or it is a normal verilog file??
    `celldefine
    module(..)
    .....
    endmoduel...
  9. Closed: a variable in sensitivity list is modified inside the always

    Hi,

    if a variable in sensitivity list is modified inside the always block will cause a simulation synthesis mismatch?

    if yes then please explain me with an example.

    It will be great help.
    ...
  10. Closed: I2C error

    High speed mode means if maximum SCL frequency is greater then the I2C maxumum frequency???

    Added after 41 seconds:

    Please explain me in more detail.
  11. Closed: ahb error master

    So if a master gets an ERROR response from a slave , it will always stop doing other transaction of the busrt?
    like if a busrt of 100 beats master gets a error response on 50th transaction it will...
  12. Closed: ahb specification problem

    Hi,

    How we check the ERROR response for a particular transaction of a burst.
    suppose my burst is of 100 and i got one error response for a address.Then how we can figure out that which address...
  13. Closed: What are the errors we can get in the I2C protocol?

    Hi,

    Can anyone tell me what are the error we can get in the I2C protocol and what are the ways to detect an error in I2C.

    Regards,
    Tauqueer
  14. Closed: divide by 5 clock

    Hi Murali,

    can u please explain it little bit more.

    Regards,
    Tauqueer
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    Closed: Latches in th design

    can you please explain me what are those special step to tackle the latches in the DFT .
    It would be great help for me to understand the problem.

    Regards,
    Tauqueer
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    Closed: DFTadvisor

    Thanks ...It is really very helpful.
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    1,568

    Closed: DFTadvisor

    Thanks for the reply but it would be good if anyone upload some labs for DFTadvisor.
  18. Replies
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    Closed: Looking for DFTadvisor Training Labs

    Hi,

    Can anyone please upload the DFTadvisor Training Labs.I am new to DFT and want to learn it.

    Thanks in advance.

    Regards,
    Tauqueer
  19. Closed: system verilog doubt

    some books are available in EDA board.
    http://electrosofts.com/systemverilog/
    http://www.doulos.com/knowhow/sysverilog/
    http://www.asic-world.com/systemverilog/index.html
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    Closed: A good book for Verilog programming

    samir palnitkar verilog book is the best.......
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    Closed: timing constraint reset synchronizer

    References are very good ...and now I got the idea why reset synchronizer used for asynchronous reset.

    Thanks alot
    Regards,
    Tauqueer
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    Closed: Why are reset synchronizers used ?

    Hi,

    Can anyone explain me why reset synchronizer used?

    And why asynchronous reset deassertion should be synchronized?

    Regards,
    Tauqueer
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    Closed: Latches in th design

    Can u please explain me like
    Why it is very difficult to perform STA with latches in the design....

    Regards,
    Tauqueer
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    Closed: Why do we avoid latches in the design?

    Why we avoid latches in the design, even if they provide only cell delay.
    Is there any time related issues??

    regards,
    Tauqueer
  25. Closed: clock latency

    Thanks for the such a clear reply.

    Thanks alot.

    Regards,
    Tauqueer
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