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Type: Posts; User: dick_freebird

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  1. Closed: Re: About can't find PDK in layout in Cadence

    PDKs pertain to physical implementation at a foundry (and
    the precursor steps of design capture / synthesis / analysis).

    vcvs is an ideal component with no physical implementation.
    It is ignored...
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    Closed: Re: Fast static CMOS comparator circuit

    Static CMOS comparators are not really good when it
    comes to Vio (t=0, and drift). That's why so many are
    clocked (that, and low quiescent power).

    If you were clever and had the die area and a...
  3. [SOLVED]Closed: Re: Trouble with frying 74LS11N AND Gate

    I'd start with simple testing of those "bad" logic ICs
    and see whether the inputs all show same IIH, IIL or
    some are "out of family" and thus suspect for damage.
    Given that you seem to be...
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    [SOLVED]Closed: Re: 12V power source without any IC.

    I'm (barely) curious why you "need" to use inferior
    technology. If I had to guess, I'd guess this is a school
    project and somebody else gets to set the boundaries
    and criticize the BOM.

    Your...
  5. Closed: Re: Design Resource For Wireless Power Transfer

    I'd start with everything you can get off of ChargEdge's (sp?)
    YouTube and related technical material. Evidently there
    are a lot of bad ideas out there, including most of the big
    names, when it...
  6. Closed: Re: Understanding LVS results (hierarchical)

    There's ports all the way down, and hierarchical means
    you are checking at levels below the top so you will see
    the ports of lower level blocks checked as the local
    network equivalence checks...
  7. Closed: Re: Does It Make Sense to Connect SMD Fuses In Parallel Instead of Using Bigger One

    Fuses -need- to get hot, to work.

    You cannot depend on current matching, and a set of
    (say) 1A fuses might fall like dominoes at 1A, 1A, 1A
    rather than 3A if there's significant...
  8. Closed: Re: Smaller die size by tighter SPICE corners?

    Not so much a thing for digital, but a big deal for analog.
    Consider a case where (say) you have an "edgy" process
    flirting with impact ionization at shorter L. Your modeling
    folks might manage to...
  9. Closed: Re: Why lib file only include FF,TT and SS

    FS and SF corners are often not "realistic" (not even as
    realistic as the sandbagged SS corner). You cannot, for
    example, get a max-spec Tox on the N and a min-spec
    Tox on the P channel devices....
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    Closed: Re: Realistic Monte Carlo setup

    Foundries and their PDKs are not to be trusted.

    If you want to discover how you're being led, try a
    simple simulation of key PCM devices that are used for
    WAT. Turn on process and mismatch,...
  11. Closed: Re: Short channel effects on Transconductance(gm).

    gm is the slope d(Id)/d(Vgs). Look at the basic ID-VG
    curve and you can see that there's a slope that's
    maximum and consistent, in the subthreshold region
    (thus maximizing gm) and it rolls over...
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    Closed: Re: Peak Power Vs Rated Power

    Cheesy low end consumer audio products, back when I
    last looked, often appeared to play games with power
    ratings. Like, yeah, you can get rated power for long
    enough to run the test, but the...
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    Closed: Re: DAC unit cap selection for SAR ADC

    Besides thermal noise you care about charge injection
    from the switches, that probably dwarfs thermal noise.
    Thermal noise formula would be a minimum starting point,
    what you find for Qsw and its...
  14. Closed: Re: Is this the reason there's so few 2 Transistor Fwd Sync Rect controllers?

    It seems to me that in olden times, the datasheets were
    also where companies would put applications information
    (National especially was good in that respect). But now
    I think they prefer to...
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    Closed: Re: Phase locked Loop Locking

    To me it looks like the loop is unstable, but you really
    do need a longer run time to be sure.

    I recommend checking the VCO tune range first, it
    looks like the vctrl needs to be nearly railed...
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    Closed: Re: BSIM4 MOSFETs models

    Wouldn't you really want to pick up a SPICE package with
    BSIM4 support "baked in"?

    If not then you have to drill into the docs for whatever
    SPICE (-type) simulator you do have, and learn how to...
  17. Closed: Re: when neg. edge flop followed by pose. edge flop both have different clock then lo

    Positive, negative edge have nothing to do with it.
    The problem is non-determinstic, non-stable phase
    relation between clocks.

    A negative edge FF followed by a positive edge FF
    will do the...
  18. Closed: Re: Seeing a crisp rectangular wave on an oscilloscope

    There's probe bandwidth and there's channel bandwidth.
    Probe BW is lower as far as I've seen (because what's
    the use of more BW than the 'scope front end can pass?).

    500pS risetime is (if you...
  19. Closed: Re: Motor dummy load resistor calculator

    While not necessarily related, or closely, I have observed
    that resistor loads do not act the same "as the driver sees
    it", as windings.

    I once undertook to defeat the traction control...
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    Closed: Re: FinFET code in hspice

    It is unlikely that any FinFET foundry has released
    these to anyone without a NDA, and very likely that
    the models are encrypted.

    That being said, you might find at least I-V curves
    and...
  21. Closed: Re: CPU, DRAM, VNAND - why can't they be integrated together on a single SoC?

    Aside from the CPU, the memories want different things.
    DRAM (optimized for cost) wants trench capacitors or at
    least capacitors optimized for areal density. Meanwhile
    "VNAND" (or any EE memory)...
  22. Closed: Re: Two polysilicon layers for gate connection

    Dual poly has been a sometime feature of mixed signal CMOS
    processes, used to make poly-poly (POP) capacitors that
    don't block metal routing. In these days of >10 metal levels
    the MIM capacitor...
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    Closed: Re: Step Down 16khz noise output on VIN

    I don't see any meaningful debugging here. Do you have an
    oscilloscope?

    I might suspect that the load dependence of this "noise"
    may have to do with the source you are powering the
    converter...
  24. Closed: Re: Synchronous Flyback is cheapest way?

    Looks like the latched OCP is all at the board level, though
    there's ideal components which are always suspicious.
    Why not make it a "motorboat" timeout (one-shot)
    instead? If the uC (or whatever)...
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    Closed: Re: VCo with disable function

    Sure. But how you'd do it, will depend on details of
    what you want from this.

    You could cut power (a load switch IC or two) and
    this would save a fair bit of current from the quiet
    VCO...
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