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  1. Closed: Laser module for detecting SMD component dimensions

    Hi,

    I saw that Cyberoptics is (or was) selling sensors for measuring SMD Component Dimensions. Does anyone know how to control such used modules? Or does anyone know an alternative how to measure...
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    Closed: Re: Need USB3 FTDI or cypress HDL code

    Cypress has sample HDL code online.

    https://community.cypress.com/thread/14764?start=0&tstart=0

    I guess there are plenty HDL examples for the FTDI part on github too.

    All of them have one...
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    Closed: Re: Good PCB Layout Designers

    it really depends on a few items, what are you trying to do?
    It depends on the chipsets, frequency (not particular on the frequency itself but also on the rise time). An edgy looking signal has a...
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    Closed: Re: Good PCB Layout Designers

    I'm in Taiwan nowadays, I never had any issue with EMC (maybe luck, or I have just studied too many competitive products well enough before I did my pcbs)?
    Although I went to a lab several times...
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    Closed: Re: Good PCB Layout Designers

    I would say just do a PCB with all the positive and negative side effects. Usually the first PCBs are based on a reference design anyway there's little someone can do wrong.

    Learning by failing. I...
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    Closed: Re: Negative Slack / Report Analysis

    my final solution was to decrease the memory. I'm sure it could be done with all the memory onboard but interconnecting blocks from different banks introduces very hard to meet delays. Routing delays...
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    Closed: Re: Negative Slack / Report Analysis

    first of all I'm using Lattice Radiant

    everything works as it is basically, the main question is just about the floorplanning and if I'm supposed to be able to influence the floorplanning.

    for...
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    Closed: Re: Negative Slack / Report Analysis

    I'm doing some more experiments with floor planning at the moment but the results are pretty bad.

    Is there any common way which is supposed to work to put an entity/architecture instance into a...
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    Closed: Re: Negative Slack / Report Analysis

    Thanks for all the hints.
    Finally it seems like the fifo is okay :-)
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    Closed: Re: Negative Slack / Report Analysis

    ... for me it is unfortunately.



    the fifo is 16 bit wide, ok I have limited it to 65536bit (done slack went down to 4ns)

    After removing some single-port-ram logic it went down to -1.745ns...
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    Closed: Re: Negative Slack / Report Analysis

    I'm just doing some generic cleanup first, replacing all the variables with signals which at the moment is 90% done.

    I think I got something wrong with the fifo before, it's 30x4k. the total of it...
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    Closed: Re: Negative Slack / Report Analysis

    I'm talented in getting things wrong... ok I have implemented this one (without pipelining it - the fifo is at 5.172ns slack now, comparing with initially 66ns that's a hugh improvement).
    The...
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    Closed: Re: Negative Slack / Report Analysis

    I have so much time in between every fifo commit so even the gray code is not really used.

    Since the buffer is not a power of 2 as mentioned regular graycode doesn't work.

    when having 7680...
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    Closed: Re: Negative Slack / Report Analysis

    Thanks for all the valuable feedback!

    the problem seems to be the fifo size calculation, the fifo is not a power of 2 it's 61440 bit that's why I'm doing the weird calculation (as I would do it in...
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    Closed: Re: Negative Slack / Report Analysis

    I have added a false_path to the reset network.
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    Closed: Re: Negative Slack / Report Analysis

    thanks.

    How is this done in the real world out there?

    I have updated the design a bit but I cannot get the slack better than -12.
    Are such things just ignored in FPGA designs if they are...
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    Closed: Negative Slack / Report Analysis

    ------------------------------------------------
    Path Begin : dcfx/fifo/d2_gray_enc_rd_addr_i_i11/Q
    Path End :...
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    Closed: Floorplanning example?

    Hi,

    can anyone recommend an FPGA Floorplanning example?
    The best would be a bad example turning to something good after floorplanning iteration.

    I just went through a software-approach of...
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    Closed: Re: Lattice Radiant Warnings list

    Hi, I'm getting a similar warning message. Did you figure out more about the problem in the meanwhile?
  20. Closed: Re: Can a gated input clock be a problem for a design?

    Hi,

    the problem was the SPI Master the raspberry pi corrupts the spi stream once it exceeds 31.25 mhz.
    I was looking at the wrong side not the FPGA was the problem. SPI is pretty easy to describe...
  21. Closed: Re: Can a gated input clock be a problem for a design?

    Hi,

    thank you for your reply.
    I guess I was a bit too fast.

    My SPI implementation itself seems to be fine, however I am messing up the timing it seems, and I'm able to break it at very simple...
  22. Closed: Can a gated input clock be a problem for a design?

    I'm trying to implement an SPI slave and I'm experiencing some issues with the ICE40up that the whole design seems to be stuck if I stop sending data from the SPI master.
    I do not see any issues in...
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    Closed: registered vs non registered?

    Hi,

    can anyone explain what that means:
    The data output of the FIFO_DC can be registered or non-registered through a selection in IPexpress. The output registers are enabled by read enable.
    ...
  24. Closed: ESD test -- Using a 2KV Mosquito bat as ESD gun?

    Hi,

    today I went to a lab for testing the EMC.
    When doing the ESD test my device started to fail (the sensor IC started to reset).

    After I went home I started to think about why the IC was...
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    [SOLVED]Closed: Re: Glitch Filter VHDL // Lattice document

    ok everything's clear now.

    I'm also implementing an I2C-slave I have used the "filtering"-way which is described in the lattice document (I'm using 3 taps), my clock is running at 12mhz.
    The...
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