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  1. Replies
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    Closed: Re: Biasing of wide swing current mirror

    It is not necessarily true that the cascode devices are bigger. They can have smaller Lc. Of course smaller the Vov of the cascodes, more headroom you have for mirror transistors. Probably the worst...
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    1,192

    Closed: Re: Biasing of wide swing current mirror

    1) In your current mirror you design your W/L mirroring transistors with certain Vov in mind, say 200mV. So, whatever voltage you apply at the gates of the cascode transistors (Wc/Lc transistors) it...
  3. Closed: Re: Input DC offset result output dc value reach vdd

    No, you don't
  4. Closed: Re: Problem in using Spectrum Function in Cadence IC6.13

    Maybe you should also do FFT and plot the spectrum. Thus you can see the harmonics and how large they are.
    Also, do you wait enough time from the start of the simulations to let things settle...
  5. Closed: Re: Input DC offset result output dc value reach vdd

    A gain of 30dB, which is about 40V/V will produce diff output of abut 4V for an offset of 0.1V. If your supply voltage is below that value or about that value, the amplifier will saturate to the...
  6. Closed: Re: Active load differential amplifier design

    When I asked about the operating point, I meant Id, which you show, but also Vov and Vds for the devices and the output DC voltage.
    Few things I notice. First, looks like you are simulating the...
  7. Closed: Re: Active load differential amplifier design

    I don't know what simulator you're using but if you can it will be much more helpful if you post a picture of the schematic with the operating point of the transistors annotated.
  8. Closed: Re: Looking for 'Introduction to CMOS OP-AMPs and Comparators' ebook

    The traditional square low equations used for hand calculations in designing analog circuits are quite unprecise when it comes to newer technologies, say below 0.18u. gm/Id methodology of designing...
  9. Closed: Re: Looking for 'Introduction to CMOS OP-AMPs and Comparators' ebook

    Yes, that's the one.
  10. Closed: Re: Looking for 'Introduction to CMOS OP-AMPs and Comparators' ebook

    Actually, the book came out somewhere in the early 2000's and by that time 0.18umm technology was already a mainstream. I don't think just the fact that the book is old can prevent you from reading...
  11. Closed: Re: Op-amp design specification for certain application

    The GBW of your amplifier really depends on the application you target. GBW of the loop gain being more or less the -3dB frequency of the closed loop response. For example, if you are using the opamp...
  12. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    Yes, of course you can achieve it. Make the flow diagram of the thing and based on it design the circuit.
    Here is a dirtier way of perhaps doing it. I did not simulate the circuit, so there is some...
  13. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    A counter by itself is a state machine. A counter the way you have done it will keep on counting for as long as there is clock. Surely you can design a counter that is triggered by your short pulse...
  14. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    Conceptually, how about you trigger the counter with the rising edge of your short pulse and let it count for as long as you need. When it is done counting, it generates a transition, say low to...
  15. Closed: Re: There is a question about 'Stability of Integrator'

    How do you provide bias to the negative input?
  16. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    100ms is a lot for an IC. If you have a clock, use a counter for the timing.
  17. Closed: Re: PMOS WELL of same bulk potential of different transistor groups

    If they really have to match. place them in the same well.
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    Closed: Re: current mirror matching issue

    You can abut them but this comes with some limitations. The width of the cascode devices should be the same as the width of M1/2 in order for this arrangement to work. Also, if you have multiple...
  19. Closed: Re: PMOS WELL of same bulk potential of different transistor groups

    It is customary to place matched PMOS transistors in the same well. And I mean physically the same well, not just electrically connected to the same potential.
  20. Closed: Re: Layout design issue of a multi branches current mirror

    From your explanation I understand that these are cascode transistors for current mirrors. If this is so, then matching between cascode transistors is not really as critical as the matching of the...
  21. Closed: Re: Input transconductance relationship ti the differential or common mode voltage

    I have personally never done this but I assume you start with the large signal equations of the differential current in the diff pair vs Vid. The you can plot the current vs Vid and even you may find...
  22. Closed: Re: Input transconductance relationship ti the differential or common mode voltage

    The formula you use is the simplest level2 square law model for the transistor. Actual models are not that simple, but for hand calculations your formula should be good. In anyway, you want to get in...
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    Closed: Re: Op-amp and compensation

    Regarding the offset: a) gains up the input referred offset by 1x, while b) gains it up by 2x.

    As to the Miller compensation: whether that parasitic cap is at the OTA node or the output node - it...
  24. Closed: Re: Parasitic capacitor extraction: huge value

    Why don't you just simulate Cgs and Cgd and see for yourself what the value is.
  25. Closed: Re: Parasitic capacitor extraction: huge value

    Before thinking about problems in RF design with these transistors, I would worry about models, their possible incorrectnes and my lack of understanding what's going on inside.
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