Type: Posts; User: timof

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  1. Replies

    Closed: Re: mosfet as a switch in 28nm technology

    Are you asking about a book on layout in general, or on power transistor layout?
  2. Closed: Re: Looking for 'Introduction to CMOS OP-AMPs and Comparators' ebook

    Analog design in advanced nodes (such as 10nm, 7nm, 5nm) is VERY different form older nodes in this sense - layout parasitics in older nodes were second order effect, and devices were playing the...
  3. Replies

    Closed: Re: Parasitic capacitor extraction: huge value

    You show schematic only, but talk about parasitic capacitance.
    Is this schematic simulation problem, or post-layout?
  4. Replies

    [SOLVED]Closed: Re: layout extraction changing device

    Try not to do any post-processing, if possible, you may create more problems.
    Most likely, your problem is caused by a mistake in the layout.

    The devices are recognized from the layout by LVS...
  5. Closed: Re: Aspect ratio of the matched transistor array

    Even if you have a single transistor, with wide gate, it is recommended to fold its gate to form a multi-finger device, with aspect ratio around 1.

    Interconnects matching is important not only...
  6. [SOLVED]Closed: Re: Can you use StarRC to extract a certain subcell and all its connections to topcel

    No, this is not possible - in StarRC, or in any other industry standard parasitic extraction tool.
    (actually, the goal as you formulated it is not well-defined - what if your net goes to other cells...
  7. Closed: Re: Post layout simulation results differ from prelayout simulation- S21 is negative

    First thing to check is - whether your inductors were extracted as R parasitics, or defined as p-cells or cells that are blackboxed for extraction.
    If it's the former - you have a big problem,...
  8. Replies

    Closed: Re: Extra layers in finfet technologies

    In FinFET technologies, the structure of device (transistors) is much more complex than for planar devices.

    So, in additional to BEOL (Back End Of Line) layers, foundry are using MEOL (Middle End...
  9. Replies

    Closed: Re: Capacitance and fringing equation

    There are many online capacitance calculators, just do a search, for example:
  10. Replies

    Closed: Re: MOS capacitor when Vgs is -ve

    Usually, accumulation layer formed by holes (in nMOS transistor) is not called a "channel" - a channel is something that allows a current flow between source and drain.

    When AC signal is applied...
  11. Replies

    Closed: Re: ANSYS Totem electromigration check

    Totem, Voltus (or VoltusFi), or any other EM / IR drop analysis tool simulates current flow in R or RC network (for power nets or signal nets).
    When it does dynamic EM / IR simulation, a current...
  12. [SOLVED]Closed: Re: Post layout Monte-carlo simulation with TSMC 180

    Why do you call "nch_mac" a mismatched model?

    From what I know, nch_mac is a macromodel (i.e. a wrapper around a transistor model, that captures some of the parasitics).

    In old nodes, like...
  13. Replies

    Closed: Re: Current mirror unpredictable behavior

    Another possible root cause for the current mismatch is IR drop on the ground net (if the two devices are not located "identically" with respect to ground net R network and its ports) - so that their...
  14. Closed: Re: The confinement effect in thin(and small width) metal tracks?

    I would say, that the height is larger than the width in lower metal layers in N7 - judging by SEM/TEM images people publish in their papers.
    But the metal height is a top secret information,...
  15. Closed: Re: The confinement effect in thin(and small width) metal tracks?

    There are several effects affecting resistivity of narrow width (and small height) wires - surface scattering, grain size and structure, cladding (liner) layer (having much higher resistivity versus...
  16. Replies

    Closed: Re: Analog Layout Finger Size

    Current density depends not only on metal line length (= poly width), but also on the current flow pattern in multi-layer metallization, that is determined by the topology of the layout.
  17. Closed: Re: DRC, LVS and PEX from GDS file using linux terminal commands

    And this Linux command should also automatically recognize and apply a proper PDK (DRC/LVS runsets, tech file for parasitic extraction, etc.) from the appropriate foundry, and also - do it all for...
  18. Replies

    Closed: Re: Shorted ground ports in Layout

    You do not have to use metal resistors or use different port names for multiple pads/ports on power/ground nets.

    In LVS, and/or in extraction, there should be a setting that would tell the...
  19. Closed: Re: What is "data type" in layer definition of PDK document

    Each layer in GDSII format is defined by two integers:

    1. Layer number

    2. Layer datatype.

    Combination of these two integers uniquely defines a layer.

    Often, different layers will have...
  20. Replies

    Closed: Re: What are the port in the digital design

    Usually, a port in a design (digital or analog) is a connection point, interface to the external world.
    It can be input, output, power supply, etc.
  21. Replies

    [SOLVED]Closed: Re: General Identity of Derivative

    d(f^2(x)/dx = 2f(df/dx) -->

    B(dB/dx) = 1/2(d(B^2)/dx)
  22. Replies

    Closed: Re: Laplace from a frequency dependent expression

    What would be the physical meaning of Laplace transform of frequency-dependent power loss function?
  23. Closed: Re: Post- simulation use calibre pex view, all parasitic capacitance connected to a n

    I am not saying that net "0" is substrate - it is a "ground".

    There should be a command in your extraction tool command file (or GUI) that defines the net name for "ground".
    You can set it to...
  24. Closed: Re: Post- simulation use calibre pex view, all parasitic capacitance connected to a n

    Net "0" is usually a (default) ground net.

    Check your extraction settings - if you want to see coupling capacitances between the nets in your post-layout netlist, you should not be grounding them...
  25. Replies

    Closed: Re: Combining PIMP in TSMC

    You are right, my statement concerning electrical connection of PIMP shapes was not correct.
    It is when "PIMP AND ACTIVE" overlap, (DC) electrical connection happens.
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