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Type: Posts; User: vyella1

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    Closed: Re: power analysis using synopsys DC compiler

    You need to run post synthesis simulation on the synthesized netlist and generate saif file first. Later load the synthesized design and libraries and give generated saif file as an input to design...
  2. Closed: Re: Output

    The synthesis tool will usually ignore is_x and will give it as a warning.
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    Closed: Re: Design compiler synthesis

    Thank you for responding Really, I am not Sam.
    Even I thought the same and I checked the log file, the retiming option is not turned on
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    Closed: Design compiler synthesis

    Hello Forum,
    I am working on RTL synthesis of an ECC Decoder(which has many sub modules) using design compiler, and I encountered a timing violation and the critical path is in sub module ABC....
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    [SOLVED]Closed: Code coverage of a design

    Hello forum,
    I am investigating on code coverage. I have a design and upon doing coverage analysis, the coverage report shows that my test bench does 70% of code coverage. Is it necessary to have...
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    Closed: synthesizing memory as latches

    Hi all,
    I am designing a decoder and my design uses memory. For some of the memory blocks I am using compiled memories and for other memory blocks I am synthesizing it as flipflops(synthesizing...
  7. [SOLVED]Closed: didn't find inverter for specified operating conditions

    Hi Forum,
    I ran a synthesis using design compiler for a using standard cell library which has operating conditions(Voltage=1.05V, Temp=25C). Now I want to run synthesis for different operating...
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