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  1. Closed: Re: Plotting of VCO output power vs frequency in cadence spectre

    google it on internet
  2. Closed: Re: Need documets related to extraction of Inductance using Cadence Assura

    Just use EM simulation. You would need an interface between Cadence (if you are using that) and Keysight ADS - it is called GoldenGate for Keysight Momentum (an EM Simulator). It can simulate...
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    Closed: Re: NCSU FreePDK 15nm for Analog Design

    There is always Cadence's General Purpose PDK's, for using the flow of their software and tools and yes, they have a FINFET GPDK.
  4. Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    i just want to learn how to do it. also not all PDKs offer "any help" or tutorials - especially on how to do layout.

    i am going to answer my own question here: i will use Microwind to learn how...
  5. Closed: CMOS FINFET Layout Tutorials/Explanations

    What are the best resources (papers, books etc) to learn FINFET layout ?

    Can anyone share any ?
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    Closed: NCSU FreePDK 15nm for Analog Design

    Hello,

    Has anyone used this NCSU kit for Analog Design ?

    Or is it mainly for digital design (standard cell flow).

    Thank you.
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    Closed: Re: Decoupling Capacitance in IC Layo

    To this point, I have a few questions.

    When doing over 10 GHz amplifier designs, I usually tend to EM simulate the supply lines to determine the amount of RLC in the DC path and then use that to...
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    Closed: Re: Decoupling Capacitance in IC Layo

    So you just add as much decoupling as you can depending on your layout at the IC level ?

    Just any amount ?

    - - - Updated - - -



    --
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    Closed: Supply Decoupling Capacitance in IC Layouts

    If doing an analog or RF layout, how much decoupling capacitance do you use in the layout for supply decoupling and, for RF layout, for supply feed line decoupling ?

    How do you calculate these...
  10. Closed: Re: Spice .INC file into Cadence Spectre/DFII

    What if I have no model file chain and this is all I am using ?
  11. Closed: Spice .INC file into Cadence Spectre/DFII

    Hello,

    I have a spice model for a process in .INC format.

    How can I use this file to do simulation using Cadence Spectre ?

    I would assume .include model.inc - but where do I add this ?
    ...
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    Closed: Length of Path in Cadence Virtuoso/DFII

    Hello,

    I have a non straight, meandered line/path in Cadence Virtuoso/DFII.

    Is there a command to measure the length of this path ?

    Thank you.
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    Closed: Incisive Intallation using Installscape

    Hello,

    Want to install Incisive add on to Cadence DFII using Installscape on Centos 6.

    Do I tell Installscape where DFII installation is already and then install Incisive ?

    Does Incisive...
  14. Closed: Re: Converting verilog code into a symbol during AMS simulation

    https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/35255/easy-way-to-connect-a-input-bus-pins-in-schematic
  15. Closed: Re: Physical Verification with TSMC65nm CRN65LP PDK

    Now I was told for my version of Calibre 2017, I have to do the following for this PDK:


    In LVS rule file add:


    LAYOUT CELL LIST pcells “rf component here*” “rf component here*”
    LAYOUT...
  16. Closed: Physical Verification with TSMC65nm CRN65LP PDK

    Hello,

    This posting is similar to an earlier posting:

    https://www.edaboard.com/showthread.php?280164-Physical-verification-with-TSMC-CRN65LP-v1-7a-PDK

    I do not have the hcells file.

    How...
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    Closed: DNL/INL Measurement in Cadence for DAC

    DNL

    https://milindsweb.amved.com/Calculating_DNL_in_Cadence.html

    INL

    https://milindsweb.amved.com/Calculating_INL_in_Cadence.html
  18. Closed: Re: INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Hello,

    Your answer is nonsense.

    In the future, please answer the question being asked.

    That's all.

    Thank you.
  19. Closed: Re: INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Thank you.

    So, I use ramp or sine wave drive to determine my output and then use your script to turn it into a histogram in Cadence/Virtuoso?

    Then I post-process that histogram plot ?

    I...
  20. Closed: Re: INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Hello,

    Thank you - can you re-post the hard copy of your setting of "ADE>Tools>Monte Carlo"? They have been removed from the original post.

    So, basically, the procedure is:

    1. Run a Monte...
  21. Closed: INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Hello,

    I want to measure the INL/DNL of an ADC designed in Cadence Spectre/Virtuoso.

    I understand the methodology: apply an ideal DAC at the output, apply a ramp signal, or a sine wave and get...
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    Closed: LDO Simulation Output Results

    I attempted to design a PMOS Pass Transistor LDO and obtained the following result.

    I set the reference voltage to about 650mv and did a DC simulation.

    The regulated voltage starts up and then...
  23. Closed: Capacitor Selection in Sigma Delta Modulators

    Hello,

    I am designing 3rd Order, Single Bit, CIFF Discrete Time Sigma Delta Modulator.

    How to select the capacitors sizes for this design ?

    See attachment.

    CT - total of ff - feedback...
  24. Closed: Opamp - Gain/Phase Margin Swept versus Variable

    Hello,

    I want to use Cadence Virtuoso/DFII to find the gain and phase margin of an opamp swept versus the load capacitance (or any other swept variable).

    So, Gain and Phase Margin on the Y...
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    Closed: EKV to BSIM Model Conversion

    Hello,

    Is it useful or possible to convert CMOS EKV Model to BSIM Model ?

    I want to use the gm/ID sizing methodology and it is better with EKV.

    What is the reason that the EKV model did not...
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