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Type: Posts; User: Ashish Agrawal

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  1. Closed: Tool inserted DFT lockup latch is not transparent in functional mode (no test port)

    Hello,

    I am using genus tool for synthesis. I have the 2 different clock domains in my design but connecting the whole design into single scan chain.
    I see tool insert a lockup latch when it is...
  2. [SOLVED]Closed: Re: FSM output function of the encoded states

    You need to declare output as state TYPE. And then simply assign the current_state to output. You don't need the output_gen process.

    You can create a pkg, where you can define the state TYPE. And...
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    Closed: Re: Why is casez preferred than others?

    One example of casez is to code a priority encoder (or servicing multiple interrupts based on priority). It makes easier to write the code, instead of writing multiple conditions using case...
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    Closed: Re: Multicycle path and metastability

    The multicycle path constraint is used between synchronous clocks (same clock or divided clock).
    If clocks are asynchronous then no need to define the multicycle path. But you can still define the...
  5. Closed: Re: How to address CDC and what methods needs to implement in this design?

    If it case 2 (clocks are synchronous) then this should be okay.
    For multibit data, you should always capture it only when you detect the rising edge of _vld signal.
    so actually _vld signal works...
  6. Closed: Re: How to address CDC and what methods needs to implement in this design?

    Case 1 : Clocks 125 MHz and 750 MHz are from different sources (async clocks).
    From module 1 to module 2, you just need a synchronizer (may be 2/3 flops) for module1_valid signal.
    From...
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    Closed: Re: Sequential Circuit Timing Analysis

    2) clock to output delay
    e to o1 : 0.2 + 0.4 = 0.6 ns
    e to o2 : 0.2 + 0.4 + 0.4 = 1 ns

    3) external setup time <= min clock period - max clock to output delay
    ...
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    Closed: Re: Sequential Circuit Timing Analysis

    1) The max. freq. would be 1/1.8ns = 555.55MHz
    5) To make the circuit work at 2.5 GHz (0.4 ns)
    5.1) Delay the clocks for output flops, so that skew will be more.
    -- for first output...
  9. Closed: Re: Is it possible to have AXI 3 complete write transaction in only one clock cycle?

    According to spec..

    • a write response must always follow the last write transfer in the write transaction of which it is a part

    I am confused about the "follow" word. Does it mean that BRESP...
  10. Closed: Is it possible to have AXI 3 complete write transaction in only one clock cycle?

    Hi,

    Is it possible to complete one AXI 3 write transaction in just one clock cycle?
    Provided This transaction has only one beat to write. And AWREADY, WREADY and BREADY are by default HIGH.
    Lets...
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    Closed: Re: Combining two async resets

    Hi ads-ee,
    Thanks for the detailed analysis.

    In my design some flops need only RESET1, some need only RESET2 and some need both. So anyway I have to synchronize both the resets separately.
    Now...
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    Closed: Re: Combining two async resets

    Does it create any problem for Scan/ATPG?
    How the OR gate is tested? Let's say if there is any stuck at fault in OR gate (combo in reset path)?
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    Closed: Combining two async resets

    Hi,

    I am having two async reset inputs to my design. If I have to OR both the resets, where should I use the OR gate?
    1. Should I synchronize(async assertion and sync deassertion) resets...
  14. Closed: Re: Need of default unique case item in State machines encoding using enum types

    I do know that "default case" will not harm. But wanted to know that if we don't put any default case then what is intended from "unique case" and "enum types"? Do they make any difference to the...
  15. Closed: Re: Need of default unique case item in State machines encoding using enum types

    Hi FvM,

    I am mostly interested to know, will tool create latches for the code I mentioned?
    I am using 2 bit logic to define 3 states using "enum". And using "unique case" statement without...
  16. Closed: Need of default unique case item in State machines encoding using enum types

    I am using system verilog to code a state-machine.
    I defined the state variables using enum types...

    typedef enum logic [1:0] {A, B, C} state_t;
    state_t curr_state, next_state;

    I am using...
  17. Closed: Metastable signal ANDed with logic 0

    Hi,

    I have an 2 input AND gate. Let's say inputs to AND gate are I1 and I2; output is Y.

    I1 is coming out of a negedge triggered flop whose clock is I2. If I make sure I1 is settled within...
  18. Closed: Re: System Verilog : understanding logic datatype

    How come output a can be equivalent to output wire logic a ? As you mentioned that for ports "wire" is implicit declaration. But how can it take "logic" implicitly until we define it explicitly.
    ...
  19. Closed: Re: System Verilog : understanding logic datatype

    Thanks for this link. But I am still confused when it comes to input ports. I have seen the RTL in system verilog which has inputs defined like below

    Input a,
    Input wire logic b,
    Input logic c,...
  20. Closed: System Verilog : understanding logic datatype

    Hi All,

    I need some help in understanding the "logic" in system verilog.
    I am familiar to code RTL in verilog but now requirement is for system verilog.
    I am confused between "logic" and...
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    Re: verilog combinational code

    Hi dpaul,

    Thanks for the reply. But I forgot to frame the full question.

    Is there any way to implement a not gate using only 2:1 Mux (without using supply 1(VCC) or 0(GND)) ?
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    Re: verilog combinational code

    I tried to fit it in the standard equation of a mux !S*I0+S*I1
    so here it goes
    !A*(!B*C*D + C*!D) + A*(!B*C + !B*!C*!D) + (B*!C*D)
    => !A*(!B*C*D + C*!D + B*!C*D) + A*(!B*C +...
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    Re: verilog combinational code

    Agree with you. But small logic which can be identified easily, needn't to go trough n lines of code. It increases the readability of code. Also it shows the effectiveness of the designer to minimise...
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    Re: verilog combinational code

    yes, your code is right (Behavioural model). But why can't you write it in more simple way.
    If you see the logic, it is nothing but Ex-or of all the bits. output is '1' when you have odd no. of 1's...
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    [SOLVED]Closed: Re: Data signal used as clock

    I have used a clock signal as data and data as clock while designing I2C block. It's a bad design practice, since we didn't have any other fast clock available so we had to use it. At our end it...
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