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Type: Posts; User: jbeniston

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    Closed: Re: DRC problem with layout in cadence 617

    Verify > Extract uses Diva for DRC, and can't use Calibre DRC rules. So you either need a different rule deck or run Calibre. (Which would be Calibre > Run nmDRC if you have it installed and setup).
  2. [SOLVED]Closed: Re: What is the difference of power estimation between Design Compiler and PrimeTIme

    Yes, you need to use a VCD file, otherwise the toggle count used for the power estimation is just a fixed value, and is unlikely to be the same as in your design. As dynamic power is proportion to...
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    Closed: Re: Digital design of a GPU

    There's an open source GPU here: https://github.com/VerticalResearchGroup/miaow/wiki/Architecture-Overview - so you can even take a look at the source code if you want.

    Have a look at the hotchips...
  4. Closed: Re: Effect of adding an BUF/INV in physical Design on LEC

    Not if they're inserted correctly.
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    Closed: Re: 32x32 Single Cycle Fast Multiplier

    Perhaps a silly question, but did you just try synthesizing assign product = multiplicand * multiplier? Design compiler has some fairly decent implementations if you have a DesignWare license. (Make...
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    Closed: Re: Tile size, gates and infrastructure

    2) Yes for the cheaper licenses. No for the full licenses. But quality of results and runtime will degrade if you try to P&R too many at a time.
    4) x64 / Linux
    5) No
  7. Closed: Re: How to Optimize power with Design Compiler

    set_leakage_optimization true
    set_dynamic_optimization true
    read_saif -input your.saif -instance_name testbench/dut -auto_map_names
    set compile_clock_gating_through_hierarchy true
    compile_ultra...
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    Closed: Re: lw, sw in a processor

    1. yes - although stores don't necessarily need to stall in a non-trivial cache
    2. yes
  9. Closed: Re: Encrypt verilog with ablity to synthesize in cadence tool

    Yes - but basically you need to encrypt it once each for Cadence / Synopsys / Mentor. Search for 'pragma protect'
  10. Closed: Re: Variable in Design Compiler for clock gating

    size_only is perhaps better than dont_touch if you want to preserve something. (You don't necessarily even need to use this will manually instanced clock gates).

    Not sure what you mean by a...
  11. Closed: Re: Variable in Design Compiler for clock gating

    Automatic clock gating can't always optimally determine when clock gating can be inserted. It's good if there is an obvious enable that can be converted, but not so good when you're gating multiple...
  12. Closed: Re: Is that possible to synthesize mixed (vhdl & verilog) design using DC ?

    Yes, providing you have the require licenses.
  13. Closed: Re: How to figure out whether it is setup or hold issue on real silicon

    Try changing voltage.
  14. Closed: Re: UPF: What is isolation sense in isolation strategy?

    The isolation signal is the signal used to control when isolation is enabled. The sense of that signal, specifies whether the isolation is enabled when that signal is high or low.
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    Re: RTL for linear search

    Try this free simulator: http://iverilog.icarus.com/
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    Closed: Re: 4 bit multiplier from 2 bit multiplier

    I can. No.
  17. Closed: Re: What is the exact use of Wrapping burst transactions in AXI 4 ?

    Critical word first cache line refills
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    Closed: Re: $20K acceptable for MOSIS?

    You can use Europractice from outside the EU. It's not as cheap as $5k-$10k though! Pricing http://www.europractice-ic.com/docs/180315_MPW2018-miniasic-v4.0.pdf

    What die area were you getting for...
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    Closed: Re: $20K acceptable for MOSIS?

    Have a look at http://www.europractice-ic.com too.
  20. Closed: Re: how to decide memory extra margin adjustment (EMA)

    Using lower than the default value will improve timing, but potentially reduce yield.
  21. Closed: Re: How to use lowVT and high Vt in 45nm technology

    In your synthesis script, simply include one std cell library for each VT.
  22. Closed: Re: [Moved]: standard cell speed dependency upon number of tracks

    12-track is larger and faster.
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    Closed: Re: Need a detailed notes on tsmc library files

    apt - Milkyway views used by IC compiler.
    nldm/ecsm/ccs - Timing libraries for Design Compiler / IC Compiler / RTL Compiler / Encounter - varying level of accuracy depending on which model you use...
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    Closed: Re: Editing synthesised RTL in cadence virtuoso

    You could try using a piecewise linear (PWL) voltage source, if in pure spice - or use Verilog-A.
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    Closed: Re: Editing synthesised RTL in cadence virtuoso

    For purely digital simulation, from Encounter, you would run rc extraction from within Encounter - and this will allow you to output a SDF file and Verilog netlist you can simulate in...
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