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Type: Posts; User: timof

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  1. Closed: Re: Lectures or textbooks related to high-speed wireline circuits and systems?

    How about this:
    ...
  2. Closed: Re: [moved] Value of lateral electric field(E0) in UMC 65 technology

    Lateral electric field in a MOSFET is not constant, it has a sharp peak near the drain.
    But I doubt that such a deep microscopic characteristic, even if known, would be used in an empirical...
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    Closed: Re: Biasing an array of current steering DACs

    And even within one DAC, make sure that the voltage drop along the ground net, feeding the current sources, does ot create too large Vgs mismatch across current sources.
  4. Closed: Re: Cannot generate calibreview pop-up after PEX

    OK, thanks.
    Indeed, some problems go away after you restart Virtuoso.
    It's probably the first thing to try, when debugging such problems.
  5. Closed: Re: Cannot generate calibreview pop-up after PEX

    Why do you need a pop up window?
    If you selected Calibre View as output post-layotu netlist format, the extraction tool should just generate it. Check your directory, for the presence of this file.
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    Closed: Re: DAC unit cap selection for SAR ADC

    A high attention should be paid to wiring parasitics - which may destroy your matching / binary weighting of the capacitors in the capacitor bank.
    Use field solver (built-in in all standard...
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    Closed: Re: Polarization MOSFET SOI

    In FDSOI technologies, adaptive back bias (voltage applied to substrate or well under BOX) is a popular and common technique to control leakage vs performance tradeoff.
    Positive voltage will lower...
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    Closed: Re: Polarization MOSFET SOI

    Questions:

    1. What do you mean under "polarized" - applied voltage, or doping type? (I think, you mean the former).
    2. What do you mean under "bulk" - body of SOI MOSFET, or substrate region...
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    Closed: Re: TSMC65nm CRN65LP PDK Calibre and PEX Issues

    This post at Mentor Communities webpage may help you:

    https://communities.mentor.com/thread/10952

    This post gives some pointers to the documentation, and explains the idea and flow.

    The...
  10. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    I agree that circuit simulator cannot be used to do parasitic extraction (calculation of parasitic elements - R, C, etc.) - there are specialized tools for that (parasitic extractors - such as...
  11. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    Parasitic elements (R, C, L, K) have the same relationship with the circuit simulator as design elements - transistors, diodes, etc.
    Their characteristics are determined by their structure (width,...
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    Closed: Re: Voltage drop of on die power gating cells

    I would think the effect of voltage drop on power switches on timing would be the same as the effects of voltage drop on the interconnects (external and virtual power / ground nets).
  13. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    From the diagram, Cpar=Cw is parasitic capacitance of the wire (more accurately - parasitic capacitance of the net).

    In distributed RC parasitic extraction Cpar may correspond to a large number of...
  14. [SOLVED]Closed: Re: Errors occurred after setting up calibre view

    Looks like a problem caused by the syntax - by the angular brackets.
    Try replacing them by square brackets.
    Different tools have different requirements on brackets (e.g. triangular vs square), and...
  15. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    This might be a problem.
    This DSPF file is valid, but nets VSS and VDD extracted as ideal nets - meaning they are represented as one node, with no parasitic resistors.
    I suspect the command in...
  16. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Good, the .SUBCKT statement looks good.
    You can also check *|NET section for nets VDD and VSS, to make sure these nets are extracted correctly - and you can then assume that the extraction went...
  17. Closed: Re: How to model intrinsic semiconductor in Sentaurus TCAD for ISFET simulation.

    What is ISFET?
    (ISFET is not a standard abbreviation, in IC design, manufacturing, or semiconductor device areas).

    In TCAD, just set the doping level at a low level (e.g. 1e10 cm-3), and you...
  18. Closed: Re: How to simulate finite charge applied to the gate of a FET in Synopsys TCAD

    If you place a charge at the "gate surface" - i.e. at the gate and the gate dielectric interface (or inside the gate or at any other surface of the gate electrode), it will be screened by free...
  19. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    In lab3 (parasitic extraction), Fig. 6 - select "Format" to be "SPF" (or "DSPF"), if it's available - and you will get a DSPF file format - a simple text file format for post-layout netlist.
    It's...
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    Closed: Re: Metal Semiconductor Contact

    1. Normally, the Fermi level of a metal is a basic material property of the bulk, so it should not change in the presence of a contact with semiconductor.

    2. No, it changes due to the image charge...
  21. Closed: Re: What things we need to take care a lenghty routing let's say 5000um

    In general, I would care about long line resistance, RC delay, capacitive coupling (accepting or introducing noise from/to other nets).

    For current paths - IR drop (because of high resistance).
    ...
  22. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    If LVS is clean, this means 1:1 correspondence between schematic and layout, and net names are matched, so VDD / VSS should be the correct net names.

    Parasitic extraction tools are very weakly...
  23. Closed: Re: Why all the applied Voltage appears across the Depletion Region ?

    Low level injection definition is - when concentration of minority carriers is lower than that of majority carriers (or doping).

    One can create a diode with very large series resistance of the...
  24. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    It's hard to tell from the snapshot you provided, what's wrong.

    What flow are you using?
    Calibre LVS / DRC then StarRC for extraction?

    Can you check if you have nets VDD and VSS on .SUBCKT...
  25. Closed: Re: Why all the applied Voltage appears across the Depletion Region ?

    Low and high are relative terms.
    It's low as compared to the diode intrinsic (depletion layer) resistance.
    It's low because of some decent level of doping (1e16-1e18 cm-3), to have series...
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