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  1. Closed: Re: Implementation error (ERROR: Place: 1500) on ISE 14.5

    Read this - https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_constraints_entry_methods.htm
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    Closed: Re: COmparator using xor gate

    @OP,

    You need to focus on what Klaus has mentioned regarding digital comparator. Do you need all those comparisons or not.
    Else a single XOR gate is a very simple 1 bit comparator in itself. ...
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    Closed: Re: MBIST clocks synchronization

    This is a question for the ASIC forum, maybe you get better answers there...
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    Closed: Re: VCS and XA Version Help_Urgent

    Not recently. But compared to 2018, 2013 would be an ancient version. Having access to a 5 year older version is also an issue and the complete tool settings environment need to be changed.


    You...
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    Closed: Re: VCS and XA Version Help_Urgent

    Generally speaking it is always better to use the latest simulator version, whether analog or digital or AMS. There are a lot of s/w improvements and bugfixes.


    Did you check Synopsys website for...
  6. Closed: Re: How to do post layout simulation during digital ASIC design?

    Generally speaking, you would take the design netlist (which will be your DUT) and instantiate it within your testbench (the same top-level testbech that was used during functional verification),...
  7. Closed: Re: Nexys video Artix-7 board - PCIe Ethernet FMC high throughput and low latency

    PCIe is preferred for high and fast data rate. But then you have the complexities of a reliably working host-side firmware that will control the PCIe.
    Then again the Nexys video Artix-7 does not...
  8. [SOLVED]Closed: Re: Vivado Synthesis failed with No errors or warnning

    I guess you have seen this failure message in the Vivado TCL console.
    Have you looked inside the synthesis log file?
    If not, you need to go through the log file carefully to find out if the reason...
  9. Closed: Re: Switching between more Bit-streams in single FPGA

    As mentioned in the above post, you can store the bitstreams in an external flash.
    On SRAM based FPGA internal memory (e.g- Xilinx FPGA), no.
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    Closed: Re: [moved] Xilinx Ethernet Interface

    That depends on how fast you want to transfer the Ethernet data. Are you clear on that?

    If you want speeds of 1G or less, then RJ45 needs to be used. For higher Ethernet speeds use the SPF cage.
  11. Closed: Re: what is the difference between @posedge clk or negedge rst or posedge rest

    Go to your institution library (unless you are restricted by covid19 lockdown in your region) and get a digital design book rather than looking for material in the internet.
    Reading a book is...
  12. Closed: Re: How to draw dotted desired rectungular box using ISIS PROTEUS 7 PROFESSIONAL

    Please read the documentation or help guide for ISIS PROTEUS 7 PROFESSIONAL. It should be mentioned there.
  13. Closed: Re: My test pattern is not like should be! Somebody can help me please?

    Hello OP,

    As I deduce that you are looking to learn about video frame buffers, see here....
    https://forums.xilinx.com/t5/Video/Xilinx-Video-Series/td-p/849583
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    Closed: Re: AXI arvalid signal issue

    Should not be. Better you ask this in the Xilinx forums.

    As for your AXI enlightenment and wisdom, I would recommend reading all the AXI related articles in this blog....
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    Closed: Re: Conflict between two axi masters.

    I cannot comment more.

    You need to check individual axi channel transactions and verify that the channel handshakes are happening properly. Maybe you can find a problem there.
    Check also the...
  16. Closed: Re: Tool for transforming python code to FPGA for Machine Learning

    Did you look into PYNQ and the libraries therein?

    http://www.pynq.io/
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    Closed: Re: Conflict between two axi masters.

    Are you expecting that the slave will give data to two masters at the same time? This cannot happen.
    The slave is connected via only 1 set of AXI bus.
    Until and unless a transaction is completely...
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    Closed: Re: AXI arvalid signal issue

    This is your investigation as you have the environment set with the slave instantiated.

    changing ARADDR to 1 also does not work, I suspect the data is not actually written, but we have BVALID...
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    Closed: Re: AXI arvalid signal issue

    So you must investigate the slave IP side.

    Questions to be asked for investigation:
    Is there valid data for the slave address you are reading?
    Are you reading from a valid address at all?
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    Closed: Re: Error :Syntax error near "module"

    Possibly...
    But the OP is using vivado 19. which makes default use of xsim compiler.
    The OP was not specific about the compiler used.
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    Closed: Re: Error :Syntax error near "module"

    Please post the error msg you get.
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    Closed: Re: AXI arvalid signal issue

    Why are you supposing, see what is written in the AMBA spec.

    Sorry to say, when a thread runs this long and you ask such a question, intuition tell me you are not reading the spec.
    This is one of...
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    Closed: Re: AXI arvalid signal issue

    As I understand it, in AXI4 all channels are supposed to be independent because of the individual handshake mechanism.

    I did not find the info in AMBA spec which says the AW and W channels should...
  24. Closed: Re: two test case clock gating check circuit & clock divide generation circiut

    Write your RTL, define the constraints (SDC) and then generate the netlist.............

    show us what you have done, where you are stuck or ask if you have a specific question!
  25. [SOLVED]Closed: Re: How to check un-clocked flops and how to trace the source point for the problem ?

    The problem shouldn't be coming to this stage. I would doubt the engineer who wrote the RTL!
    How can the person write an RTL such that a clock is not connected to a flop?
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