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  1. Closed: Re: System Verilog error VLOG-13069 from Questasim with unpacked array

    dave_59 in post #2 mentioned the indices were swapped, you must have misread the line.
  2. Closed: Re: System Verilog error VLOG-13069 from Questasim with unpacked array

    No the numbers just represent the bits for a specific array entry they aren't hex digits. I though the widths of the bits and the descriptions would be enough to be clear what I was showing, I guess...
  3. Closed: Re: System Verilog error VLOG-13069 from Questasim with unpacked array

    using the following example arrays:

    logic [3:0] bt1[7:0];
    logic [3:0][7:0] bt2;
    logic [7:0][3:0] bt3;


    The bit definitions of the arrays are:
  4. Closed: Re: Problem in reading W5300 registers with Spartan6

    Using a DCM is better as the tools will place the clocks on dedicated routes from the DCM to the global buffers. Also use the global buffer output as the feedback path you can remove the clock...
  5. Closed: Re: Laptop RAM upgrade (new RAM doesn't work in RVS slot, but works in STD slot)

    std_match, When I did a quick search yesterday I noticed that there was conflicting information on the RAM required (DDR3L or DDR4) for a 15-ay013dx, so they probably didn't check their HP...
  6. Closed: Re: Problem in reading W5300 registers with Spartan6

    Where is your testbench? Did you just compile this code and try it on hardware without running it in a VHDL simulator?

    One thing I do notice, you are using clock dividers, which are not a good...
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    Closed: Re: AXI arvalid signal issue

    That doesn't look right, any of the valid signals (from the master) should not be using the ready (slave) status to determine if the valid should be asserted.

    The de-assertion of valid does look...
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    Closed: Re: Recommendations for Beginner

    Tasks are only slower in Vivado if you don't script the flow or use the Tcl command line to do everything. Vivado when run exclusively using the GUI, unloads the database after each step. This...
  9. Closed: Re: how to generate 4MHz clock from 2 MHz clock.

    Must be a Xilinx part (MMCM/PLL), but can't tell which one as more than one of the families has that primitive. Though it can be narrowed down with the OP's statement that the wizard says the FPGA...
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    Closed: Re: Recommendations for Beginner

    I think it's an opinion based on smaller parts, for the largest parts in the Xilinx family ISE was very slow due to the extremely large memory requirements and the database design that wasn't very...
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    Closed: Re: SERDES termination methods

    If you are looking for the standard. SERDES uses CML or Current Mode Logic. The term SERDES describes the upper layer protocol for the Serilaizer and Deserializer.

    You can have SERDES that uses...
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    Closed: Re: Who has experience using tube...

    I find the dichotomy of a modern printer (and cables) in what looks like a picture from the 1930s kind of interesting. Even the crowbar looks like it could be hand forged.
  13. Closed: Re: How to create an IP core based on a project in ISE?

    You run the design through XST synthesis.
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    Closed: Re: AXI arvalid signal issue

    Asserting valid based on ready can result in a deadlock issue as neither side ever asserts their respective signal based on waiting for the other side to assert theirs first. That is why the spec say...
  15. Closed: Re: SMPS based power supply for Raspberry PI 3 Model B

    Still USB-B connectors (not just the cables) are not rated for more than 30V 1.8A. Hence why I mentioned previously that the fast charging for USB uses a higher voltage and keeps the current at 2A...
  16. Closed: Re: SMPS based power supply for Raspberry PI 3 Model B

    USB type b cable was never meant to supply 3A let alone 3A to two different device at the same time (6A), a standard usb cable is good for maybe 1.5A and those shipped with cell phones that have fast...
  17. [SOLVED]Closed: Re: Design not simulating for different technology node

    It's highly dependent on the quality of the standard cell library engineer writing the code.

    It's not an ASIC library but Xllinx has had issues with having junior engineers writing their primitive...
  18. [SOLVED]Closed: Re: Take different output value from array every clock cycle

    bking, you won't get a multiple driver warning, as the VHDL loop is unrolled and only the last assignment Sub_M <= w(addi-1); gets assigned.

    OP what you wrote does this.
    process (clk, en)
    begin...
  19. Closed: Re: How D flip flop can hold output until next clock cycle when it is level firered.

    This sure looks like homework...

    Look over you notes, I'm sure they instructor must have discussed master-slave d-flip flops. Use google and find information on the circuit that implements that.
  20. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    You shouldn't be asking for a pre-compiled library you should be requesting the source file that contains the missing module. For modelsim the library database is tied to the version.
  21. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    Did a search of the entire Microsemi directory for 12.3 and that module doesn't exist (nor does it exist in an earlier version). I suspect the file that has that module (it's not a primitive) is on...
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    [SOLVED]Closed: Re: VHDL Simulation error using Xilinx ISE14.7

    Tricky thanks for the explanation, though it makes me think Verilog math is really inherently easier, at least in Verilog you have to handle overflow bits, width, sign extension, etc all on your own...
  23. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    Given you seem to have all the appropriate libraries compiled, what exactly are the errors you get on those block designs and FIFOs? Can you post the errors.

    You never mentioned if you compiled...
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    [SOLVED]Closed: Re: VHDL Simulation error using Xilinx ISE14.7

    These statements seem to mismatch



    The code comment says correct value may overflow, which means the result of c+d may be truncated (carry is lopped off or truncated) or am I misinterpreting...
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    [SOLVED]Closed: Re: VHDL Simulation error using Xilinx ISE14.7

    Nice to know, I primarily use Verilog and Systemverilog, and only occasionally am forced to use VHDL. So I'll assume that VHDL truncates the word to the longest operand and then assigns that...
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