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  1. Closed: Unable to allocate all 2GB of DDR4_PL in ZCU106

    Dear all,

    I have a block design targeting a ZCU106 board.

    I have used the Zynq UltraScale+ MPSoC to realize the Processing System and XDMA Bridge to PCI Express to implement PCIe.

    I put a...
  2. Closed: What does CPU_RESET pin exactly do in ZCU106 MPSoC board?

    Hi,

    I am using ZCU106 MPSoC evaluation board in my designs.

    Looking at the ZCU106 User Guide, there are multiple reset pins:

    PS_PROG_B : This action clears the programmable logic...
  3. Closed: Where is a high-frequency clock capable IO pin in ZCU106 board?

    Hi Guys,

    I am working with Vivado 2018.2 targeting a ZCU106 board.

    I am wondering whether there is a high-frequency clock capable IO pin available on the ZCU106 board that I can send out a...
  4. Closed: Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    Thanks @Nikiki for your reply. Can you please elaborate more on this sentence : "make a connection between data stream from DDR to the data buffers inside Zynq"

    What do you mean data stream from...
  5. Closed: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    Hi,



    I am working wothCicado 3017.3 targeting a zc706 board.



    I am trying to write some data in the DDR3 of PL and then use AXI DMA (or CDMA, I am a liitlebit confused which one) to...
  6. Closed: Number of configuration bits used by design in Vivado

    Hi,



    I am using Vivado 2017.3 targeting a Zedboard with a Zynq FPGA.



    I have designed and implemented a design and generated the bitstream that works properly. I am wondering whether it...
  7. Closed: Re: How to perform Flash Programming of the ZC706 with our own design files and bitst

    Hi niciki,
    Such a nice explanation! Thank you! I learnt from that. I have encouraged and marked your post as "helpful" becuse you helped me out by your descriptions.

    Bests,
    Daryon
  8. Closed: Re: How to perform Flash Programming of the ZC706 with our own design files and bitst

    Hi
    Thank you for your reply and nice explanation. Just as a question, should we generate the following files every time in our design or they are some pre-built files and can be downloaded and used...
  9. Closed: Re: How to perform Flash Programming of the ZC706 with our own design files and bitst

    Hi,
    Here are my steps and the relevant printscreens:

    1. Implemented design in vivado and generated bitstream

    2. export hardware including bitstream and launch sdk

    3. Create new application...
  10. Closed: Re: How to perform Flash Programming of the ZC706 with our own design files and bitst

    Hi,
    I already saw that page. In that threat, the user tried to run the TRD design offered by Xilinx including their own BOOT>BIN and .elf files. I already could do it successfully. I am trying to...
  11. Closed: How to perform Flash Programming of the ZC706 with our own design files and bitstrea

    Hi friends,



    I am working with Vivado 2017.3 targeting a ZYNQ ZC706 board.



    I followed the procedure for flash programming of the ZC706 through SD Card in page 13 if this document, and...
  12. Closed: In ZYNQ FPGA : Who is controlling the AXI Memory-Mapped to PCI Express module?

    Dear all,



    Previously, I was working with Kintex-7 KC705 FPGA board where I was emplyoing the AXI Memory Mapped to PCI Express module with Microblaze to read/write data from/to PCI. Now, I...
  13. Closed: Re: Why AXI DMAreads only 16 bit from DDR3 instead of 32 bits in my design?

    @std_match,

    Thanks for your reply. The logic of your hint is correct. The AXI DMA wants to read from DDR3 through MM2S port and write into the BRAM through S2MM port. While I did your hint, I...
  14. Closed: Unable to grab PCIe ref_clk for the axi_pcie in ZC706 board !

    Dear all,


    I am working with Vivado 2017.2 targeting a ZC706 ZYNQ FPGA Board operating on an Ubuntu 16.4 Linux Machine.


    Previously targeting a Kintex-7 KC705 Board, I was able to choose...
  15. Closed: Re: Why AXI DMAreads only 16 bit from DDR3 instead of 32 bits in my design?

    Dear @ads-ee,

    Thanks for your reply. AS far as I see in my searches, AXI BFM stands for AXI Bus Functional Model which is available also for the Zynq. However, I could not find any link to order...
  16. Closed: Re: Why AXI DMAreads only 16 bit from DDR3 instead of 32 bits in my design?

    Isn't there any experience or hint in this regards?
  17. Closed: Why AXI DMAreads only 16 bit from DDR3 instead of 32 bits in my design?

    Dear all,



    I am working with Vivado 2017.3 targeting a KC705 evaluation board (with Kintex-7 xc7k325ffg900 FPGA).



    I have block design omprised of a DDR3, an AXI DMA and a BRAM...
  18. Closed: How to transform this design into KC705 using a Microblaze?

    Hi,



    FYI : I am using Vivado 2017.3 targeting a KC705 board including a Kintex-7 (xc7k325t) FPGA.



    I am trying to read data from DDR3 and load it to a FIFO and then send the read data...
  19. Closed: Re: Is it possible to fetch data from DDR3 and feed it to JESD204B?

    Any help or advice here?
  20. Closed: Re: Is it possible to fetch data from DDR3 and feed it to JESD204B?

    Hi,

    For the simplicity, I put a snapshot of my block design based on your advice.

    Now, Can anyone let me know am I missing something?? How can I create the link between DDR3, FIFO and JEAD204?...
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    Closed: Re: Change my username please

    Dear ads-ee,

    Thank you very much for your extended and complete description. I completely do agree with you. You were always helpful to me in this forum, either in high-tech electronic questions...
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    Closed: Re: Change my username please

    Dear KlausST,

    Thanks for your explanation and pointing me out to the forum's rule. I did not know the guys are not active anymore in the forum. Changing the username is not a big deal for me at...
  23. Closed: Re: Is it possible to fetch data from DDR3 and feed it to JESD204B?

    Hi @Shaiko,

    Thanks for you good explanation. Just as a question, by this implementation, where would be the location for DMA IP and how should I connect it in my design?

    Bests,
  24. Replies
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    Closed: Re: Change my username please

    I am not telling stories....!!!!! I had a question from the "admin" of the forum, that's all ! If you do not know the answer. no one asked you to contribute in responding with an uncertainty answer...
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    Closed: Re: Change my username please

    Andre,

    Why did they do it for lots of users if it is not within the forum policies?
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