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Type: Posts; User: skyworld_cy

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  1. Replies
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    Closed: Re: DFT issues on scan clock input as "x"

    Hi,
    this is a synthesis process with DFT insertion, which I don't think it is a simulation. I just use design vision to trace why dft_drc reports these warnings. The input scan clock becomes to be...
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    585

    Closed: Re: DFT issues on scan clock input as "x"

    Hi,
    I just confused. If the gate cell gated the clock input, why the buffer input which connects to input port (pma5ck), is also "x"? I set this port as scan clock input port in script:
    ...
  3. Replies
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    585

    Closed: DFT issues on scan clock input as "x"

    Hi,
    I'm learning DFT and trying to finish my design with DFT compiler. After I run command "dft_drc" in DesignCompiler, I found thousands of warnings on clock as "Clock input CP of DFF xxx was not...
  4. Closed: Re: I can't find the wrong piece of code for signed calculation in verilog

    Thank you for your kind reply. I will check this.

    - - - Updated - - -

    Hi FvM,
    I have read your post and have one question: sign_a has a range of -256 to 255. This sign_a compares with 10'd511,...
  5. Closed: I can't find the wrong piece of code for signed calculation in verilog

    Hi,
    I wrote a piece of code to test signed calculation. The code doesn't work as what I expected, I can't find the souce of bug. Can anybody give me some help? thanks.

    here is the code:

    wire...
  6. Closed: set_output_delay with negative value for min

    Hi,
    I always confused by those negative values set for set_output_delay. I have scanned those related threads in this website, but still confused. Can anybody give me a reasonable explanation, such...
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    2,418

    Closed: Novas verilog question

    hi,
    I'm working with Novas and ncverilog together to dump waveforms. It is strange that the log always shows this message:


    Can anybody help me to find the reason why this would happen? Thanks.
  8. Replies
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    1,549

    Closed: how to extract design hierachy in irun?

    Hi,
    I have a design with Verilog, simulated with irun. Is there a way to extract the hierarchy of the design? I would like to extract all ports of each level and probe them. thanks.


    regards...
  9. Closed: how to deal with glitches in the post simulation for PAD or gates

    Hi,
    I'm running post simulation with incisive tool, but always be headache to deal with those glitches for pads. The pad always has big delay while the signals period is smaller than it. I have...
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    1,197

    Closed: Re: set_input_delay to output pins

    Is there anybody else could give me some help? thanks
  11. Replies
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    1,197

    Closed: Re: set_input_delay to output pins

    I'm totally confused
  12. Replies
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    1,197

    Closed: Re: set_input_delay to output pins

    of course I should write all timing requirements. But is it correct to set input delay to the register left?
  13. Replies
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    Closed: Re: set_input_delay to output pins

    if I name register on the left of combo logic as reg_left, and the other as reg_right. Do you mean I should do set_input_delay to reg_left/Q? If this is right, does this mean the input delay set to...
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    1,197

    Closed: Re: set_input_delay to output pins

    Could you please give an example to make it clear? thanks.
  15. Replies
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    1,197

    Closed: set_input_delay to output pins

    Hi,

    in which case can one set_input_delay to output pins? I just met a case: In top level there are two submodules, I just found the scripts set_input_delay to one of submodules' output pin. Can...
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