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    Closed: Re: dft-how to use .bench format

    Seems that some people are working with .bench files in the same time frame.
    Similar post in the Xilinx forum: https://forums.xilinx.com/t5/Design-Entry/bench-file/m-p/997165#M21159

    I think that...
  2. Closed: Re: Attempting to get a license for feature 'Synthesis' and/or device 'xcvu440'

    Adding the ads-ee comments from above....
    Xilinx ISE is for Series6 and previous versions of FPGAs.
    If your target FPGA has changed, so should your Xilinx tools also.

    I am pretty much sure...
  3. Closed: Re: Issues during attemp of implementation of "Matrix multiplification" Verolig proje

    Yes, use Core Generator to generate.

    Otherwise consult the Xilinx ISE Synthesis guide in which there probably are RTL templates which infer BRAM.
  4. [SOLVED]Closed: Re: Request for clarification: multiplication and hardware multipliers blocks

    Read the UG901 first.

    Using the operator * will infer the DSP48 block (not sure if it is also DSP48 for Spartan3, but will be a similar block). However if you still want to be sure, use the...
  5. [SOLVED]Closed: Re: Request for clarification: multiplication and hardware multipliers blocks

    Yes the internal MUL block of the FPGA will be inferred.
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    Closed: Re: vivado post route simulation problem

    The OP finds a mismatch b/w func sim & post-impl sim. I found out he has no constraints file and still performing post-impl sim. Is it correct to perform a synth & pst-impl sim without design...
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    Closed: Re: Help in understanding innovus

    innovus tool should have a user reference manual, you can refer there for details.
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    Closed: Re: vivado post route simulation problem

    Your synth log says there are no timing constraints for your design.
    What are you trying to do?
  9. Closed: Re: Verilog wire vs reg. Which one should I use and when / why?

    Yes I meant that.
  10. Closed: Re: Verilog wire vs reg. Which one should I use and when / why?

    A reg used inside an always block leads to the inference of a flop. You use it when you are defining sequential logic.

    When you are writing RTL for combinatorial logic, something outside the...
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    Closed: Re: vivado post route simulation problem

    That's doesn't look like the complete synth log file.
    Look into project_name.runs/synth_1/runme.log
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    Closed: Re: vivado post route simulation problem

    A synthesis log is always generated by Vivado. Have you checked that thoroughly? That's a fiest check.
    Can you see the signal d[0:7] there?
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    Closed: Re: RS232 Spartan 3E testing

    Assuming your design is functioning properly, a common problem is baud rate matching.
    Make sure the rate at VHDL UART and your PC console application is the same.
  14. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    1. Get a repo, SVN, Git -- best solution!
    2. Get a filelist or .f file (tracking of files possible but not their contents). More details here -...
  15. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    I am seeing what you have written and it includes none of your project files. So I find it difficult to answer your question.
    What if you remove the file in question from Modelsim project, add it...
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    Closed: Re: Import chipscopes data to matlab

    Sorry, my bad......didn't read #1 thoroughly.
  17. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    What happens if you use the absolute path inside the RTL?
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    Closed: Re: Import chipscopes data to matlab

    I don't use Matlab!
    So I jst gave the basic idea of using scripts. Now if it can be done in Matlab, good for the OP.
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    Closed: Re: Import chipscopes data to matlab

    Just write a script in your fav scripting language (Bash, Perl, Python) which will read the txt file you have posted and write out the desired file to be read by MAtlab.
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    Closed: Re: Not enough IOB of a certain FPGA

    Hello OP,



    This looks like an internal module design to me. At the peripheral you don't have these many signals.
    If you provide us the project details then perhaps there can be more help.
    ...
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    Closed: Re: Vivado Timing Constraint

    It is Xilinx Design Constraint (.xdc) not "Vivado Timing Constraint ", which constrains the FPGA design as stated above.
    Read the latest version of UG903 for details on XDCs.
  22. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    Make sure the core is regenerated and the new one is used in your project.
    From the IP Sources tab, for the FIFO IP, also verify under Instiantiation Template, that in the generated *.vho file, the...
  23. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    You change the depth & width parameters to get the FIFO size of your choice in Vivado. These options are typically in the 2nd tab, under 'Data Port Parameters' field.

    153532
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    Closed: Re: FPGA ASIC gate count

    Can I know the ASIC gate count of Spartan-6, Artix-7, Kintex-7 and Kintex ultrascale+.

    Gate equivalent is an ASIC terminology and not related to FPGAs. FPGAs are basically composed of LUTs, Flops...
  25. Closed: Re: TC34725 i2c color sensor not working without any error (basys3 vhdl)

    It is in principle a I2C slave. So you take a slave i2c module (your sensor), connect it to a master i2c module (your logic which will acquire the data from the sensor) and put the whole thing in a...
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