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Type: Posts; User: matrixofdynamism

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  1. Closed: Can a transformer be used to convert single ended signal to differential signal?

    Can a transformer be used to convert a single ended signal to differential signal?
    If yes, then how? and why would one use a transformer instead of an opamp or some other method?
  2. Closed: Do switching regulators require a lot of external components to work?

    I was looking at schematic of the DE2-115 Altera FPGA development board. The purpose was to look at example of how te power delivery system has been designed in it.

    I found that they are using...
  3. Closed: How is Vcc plane for boards with multiple supply voltages designed?

    A Vcc plane in PCB is where the supply plane is connected to the supply voltage, similar to how it is done with the GND plane.

    Complex digital devices e.g FPGAs may have atleast 3 or more supplies...
  4. Closed: Re: Is there such a thing as an online BOM processor?

    Ok, what you are saying is that we use custom fields in the schematic or the library part itself, which shall define details of how to order it like manufactuer name, part number e.t.c and then when...
  5. Closed: Re: Is the "Gaisler method" of writing "structured VHDL" popular?

    When I did course in VHDL at my job (it was Doulos Comprehensive VHDL and very expensive), they did not actually teach the Gaisler method. Only for state machines they emphasized that the sequential...
  6. Closed: Is the "Gaisler method" of writing "structured VHDL" popular?

    I have come across the idea of "A Structured VHDL Design Method" by Jiri Gaisler. It basically proposes a certain style of describing hardware using VHDL in which we always split the hardware block...
  7. Closed: Is there such a thing as an online BOM processor?

    The BOM contains list of parts that shall be used to assemble the application PCB. It will aslo contain the manufacturer part number and package type.

    Is there service where a person can upload...
  8. Closed: Re: What are the pros and cons of using logic elements to implement FPGA memory block

    Actually there is a slight confusion on what constitutes "small" and at what point it is not small anymore. Certainly it is down to judgement based on experience.

    I had a problem where data comes...
  9. Closed: What are the pros and cons of using logic elements to implement FPGA memory blocks?

    FPGAs contain memory blocks inside the logic fabric. However, it is also possible to implement a memory block using the device logic itself. It is better to use the built in "hard" memory blocks as...
  10. Closed: Re: How does DQS make it possible to reach higher data rates in DDR DRAMs?

    But the data must reach the other end before the next clock edge, isn't it? Why can't we just use clk?
  11. Closed: How does DQS make it possible to reach higher data rates in DDR DRAMs?

    SDR DRAM does not have DQS signal, this is called data strobe and data is called DQ. On the other hand, DDR RAMs have DQS signal which makes them somehow achieve higher data rates.

    A single DQS...
  12. Closed: Re: VHDL: How to create type for unconstrained array for entity port

    Yes, but where to declare the type? In a package? If I declare it in a package then how to make the generic called word_len to reach the package so the inner dimension of the p_in_t can be...
  13. Closed: VHDL: How to create type for unconstrained array for entity port

    Here is the entity:


    entity col_piso_sr is
    generic (
    word_len: natural := 8
    );
    port (
    p_in_7: in std_logic_vector(word_len-1 downto 0);
    p_in_6: in std_logic_vector(word_len-1...
  14. Closed: Re: Can one force ModelSim to flag signals with multiple drivers?

    Its just that the synthesis tool from Altera (now Intel) takes so much longer than ModelSim to do its job
  15. Closed: Re: Can one force ModelSim to flag signals missing signals in sensitivity list?

    These answers are helpful. I learnt that the process to generate next state is combinatorial and thus should have its own process. It is a "good practice".
  16. Closed: Can one force ModelSim to flag signals with multiple drivers?

    Signals that have multiple drivers (by mistake of course) may look fine in simulation sometimes and become X at other times. When one tries to synthesize the code, it will always be flagged up as...
  17. Closed: Is there special way to map address to SDR SDRAM?

    SDR SDRAM like other DRAMs contains banks, rows, columns. Thus, to get maximum efficiency, I assume that there would be some non-trivial way to translate memory address to bank, row and column...
  18. Closed: Re: What determines the number of rows in an SDRAM?

    So it is an arbitrary choice of the SDRAM designers? I see.
  19. Closed: What determines the number of rows in an SDRAM?

    SDRAM is divided into banks, each bank into rows and each row into columns. What determines how many rows will be there in an SDRAM?
    Is there a formula used to go from a single memory location...
  20. Closed: Can one force ModelSim to flag signals missing signals in sensitivity list?

    In VHDL we often use processes not trigerred by clock e.g next state process for FSM. In this case, there may be a long list of signals that must be put into the sensitivity list.

    I have noticed...
  21. Closed: What is difference between row and page in SDRAM?

    An SDRAM consists of multiple banks, we have to "open" one row in bank at a time for reading and writing and then "close" it by doing precharge. I am trying to understand how it all comes together...
  22. Closed: What to do if Nios II program does not fit into on-chip memory?

    Tutorials teach that we use on-chip memory to store the Nios II application program. However, what to do if we do not have enough space on it? What off chip options do we have?
  23. Closed: How to find direction of signal travel in a given circuit?

    I am analysing signals used by a game console to communicate with a controller. I want to find out which signals are unidirectional and which way they communicate and which signals are bidirectional...
  24. Closed: What does it mean to pipeline a multiplexer, how is it done?

    For very large multiplexers in FPGAs, there will be a huge propagation delay that may create a critical path and cause timing violation.

    Therefore, one possibility I assume is to use multicycle...
  25. Closed: Re: Must one known SystemVerilog to use Avalon Interface Bus Functional Models?

    I have not used BFM yet since I thougt that SystemVerilog is required as they are written in SystemVerilog and I have no idea how they can be used from VHDL testbench.

    Anyway, is it also not...
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