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Type: Posts; User: promach

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  1. Replies
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    Closed: Re: AXI arvalid signal issue

    See this internal VHDL source code generated by Vivado AXI BRAM controller IP

    addra_bram_addra_i is not driven at all

    https://i.imgur.com/wsnRlXV.png
    ...
  2. Closed: Simple CMOS Analog Square-Rooting and Squaring Circuits

    For Simple CMOS Analog Square-Rooting and Squaring Circuits , how to derive equations 13 and 16 ?
  3. Replies
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    Closed: Re: AXI arvalid signal issue

    I know what is wrong. Internal BRAM_en signal is not asserted but what actually caused this ?

    Something is very wrong. clk and reset signals have been connected correctly in the module...
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    Closed: Re: AXI arvalid signal issue

    Is it true that XILINX AXI slave IP does not support simultaneous two-way data transfer ?

    In other words, for different AWADDR and ARADDR, AW* channel cannot be active when AR* channel is active ?
  5. Replies
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    Closed: Re: AXI arvalid signal issue

    That is why I never provide code to ask about the wrong AXI waveform until someone asks for the code. And data loopback test is already a SMALL testcase.

    From my personal AXi experience with...
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    Closed: Re: AXI arvalid signal issue

    See https://gist.github.com/promach/251cbb3c9c9af401bf712dc4ccb76fb3#file-read_instructions-v

    I have two AXi interfaces. I am only testing the one of the AXi interfaces.

    `define LOOPBACK 1
    ...
  7. Replies
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    Closed: Re: AXI arvalid signal issue

    changing ARADDR to 1 also does not work, I suspect the data is not actually written, but we have BVALID asserted and BRESP is ok

    Something is very very very wrong.
  8. Closed: Re: Bandstop Filters With Extended Upper Passbands

    But that wikipedia link does not mention about θ ?

    Please correct me if I miss anything.
  9. Closed: Re: LDO transient performance enhancement circuit understanding

    Look at Vin SINE() parameters
  10. Closed: Bandstop Filters With Extended Upper Passbands

    I have a question on Bandstop Filters With Extended Upper Passbands

    What does it exactly mean by θ ?

    https://i.imgur.com/nN63sbP.png
  11. Closed: Re: LDO transient performance enhancement circuit understanding

    https://i.imgur.com/3HsdZqd.png

    https://i.imgur.com/erxCSNT.png

    Note: output load capacitance, CL = 1uF

    and changing Vin parameters such as 3.3V to 2.5V , as well as lowering the Vin...
  12. Closed: Re: LDO transient performance enhancement circuit understanding

    maximum = 5V , minimum = 2.5V

    https://user.eng.umd.edu/~newcomb/courses/spring2010/303/tsmc180nmcmos.lib also resulted in similar noise issue.
  13. Closed: Re: LDO transient performance enhancement circuit understanding

    At lower supply voltage such as 2.5V , LDO does not work anymore.

    I am using this mosfet model

    What do you suggest ?

    I am not sure if FreePDK15 model could actually be used with LTSpice
    ...
  14. Closed: Re: LDO transient performance enhancement circuit understanding

    Why does the transient simulation around 10us have a lot of noise ?

    Where is the actual root cause for such deterministic noise at 10us after simulation starts ? And any idea how to eliminate it...
  15. Replies
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    Closed: Re: AXI arvalid signal issue

    The slave is a Xilinx AXI BRAM IP core



    Yes
  16. Replies
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    Closed: Re: AXI arvalid signal issue

    See AWADDR at t=60ns and WLAST at t=210ns

    also ARADDR at t=235ns

    do you guys notice anything wrong with the AXI waveform before t=235ns ?

    BRESP also returns 0 which is okay at t=220ns
  17. Replies
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    Closed: Re: AXI arvalid signal issue

    My AXI burst write transactions had zero AXI protocol violations.

    However, during my data loopback test, Xilinx AXI BRAM IP slave returns me unknown RDATA highlighted in red colour in the...
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    Closed: Re: AXI arvalid signal issue

    I do not have any more AXI violations since pc_status bits are all cleared as shown in the following simulation waveform.

    Now, I am left with the issue where AWREADY from AXI slave is kept low for...
  19. Replies
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    Closed: Re: AXI arvalid signal issue

    I wish to, but AWADDR cannot be set to be word-aligned for my code application.

    I do not think WSTRB depends on AWSIZE, am I right ?
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    Closed: Re: AXI arvalid signal issue

    YES !

    I am trying to put the relationship between the above variables in actual coding.

    awlen is enough to determine wstrb. So, why is awsize in the equation as you suggested ?
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    Closed: Re: AXI arvalid signal issue

    I suppose that WSTRB is only used in W* channel , not in AW* channel ?
  22. Replies
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    Closed: Re: AXI arvalid signal issue

    I suppose AW (address) channel is independent of WDATA ?
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    Closed: Re: AXI arvalid signal issue

    I do not quite understand the following burst alignment mechanism

    https://i.imgur.com/lrF6N9g.png
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    Closed: Re: AXI arvalid signal issue

    Why if AWADDR is set to 3 , then WSTRB should be 0x1FFF or 0xFFF8 ???
  25. Replies
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    Closed: Re: AXI arvalid signal issue

    Ok, I have solved the above pc_status[32] AXI_ERRS_BRESP_WLAST error.

    Now, I have an entirely different pc_status[22] AXI_ERRM_WSTRB issue.



    What does it mean by The information on the...
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