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Type: Posts; User: barry

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    Closed: Re: Design a system clock monitor in verilog

    Wait, you want to monitor a clock with ITSELF? Either I don't understand your question, or you're on a fool's errand. Maybe you need to restate what you are intending to do.
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    Closed: Re: Difference circuit not acting as expected

    You don’t really give us a lot of information. Like WHAT your opamp is—Don’t you think that’s an important bit of information? And Power supplies? And you know that ECL needs to be terminated, right?...
  3. Closed: Re: How can I measure AC current with ~500 kHz frequency?

    A multimeter is not going to work at 500khz. I think you want to look at a current transformer. Without further information, it’s difficult to make a suggestion. Is this for occasional measurement?...
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    [SOLVED]Closed: Re: Ground plane in audio amplifier?

    The amplifier is obviously unstable. But is it because of the plane? Perhaps the additional capacitance of the plane is the problem. You need to analyze the circuit a little more closely, considering...
  5. [SOLVED]Closed: Re: How to generate a sine waveform using a STM32 Nucleo-64?

    You can also generate a sinewave with a lookup table and counter (DDS). You don't have to use rational functions. But that 1MHz DAC will be a problem...
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    Closed: Re: vhdl problem debug help please

    I, for one, never use separate clocked/combinational process for state machines. I know all the literature says this is the way to do it, but I find it's always a problem (just like what you're...
  7. [SOLVED]Closed: Re: How to generate a sine waveform using a STM32 Nucleo-64?

    You're going to have a pretty rough sinewave since the maximum sampling frequency you can have is 48MHz. (Not even sure if the onboard DAC can run at the frequency).
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    Closed: Re: vhdl problem debug help please

    You need to have "count<=count+"01" in a clocked process, not a combinational process.

    And have you included ieee.numeric_std? Have you observed the value of "count"? Is it incrementing? Probably...
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    Closed: Re: Logic duplication and optimization

    I disagree. If there is ANY optimization, your intermediate sum, "a+b", is going to be optimized away. If you keep that intermediate sum for the sole purpose of seeing it in Chipscope, you're not...
  10. Closed: Re: Properties of material ( silver and copper )

    ALL the properties? Maybe you could narrow it down a bit; like electrical properties or mechanical or chemical properties or crystal structure or thermal properties or...

    Or, better yet, try this:...
  11. Closed: Re: NPN having its VBE protected against reverse voltage....but unecessary?

    I suppose if the output (emitter) is sitting at some positive voltage and the opamp output suddenly went to zero you’d have a reverse bias. But why don’t you ask your contractor to explain it? Aren’t...
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    Closed: Re: structure and function

    I'm not really a C guy, but that is not a function, it's a structure. Two totally different things. Look it up.
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    Closed: Re: Timing constraints using a PLL.

    The phase of the PLL is relative, either to its input clock or a secondary output clock. Once you route those signals, with no constraints, there’s no guarantee that phase stays the same. It’s like...
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    Closed: Re: Timing constraints using a PLL.

    This is NOT a good method. What may work for one build may not work for the next. Change one little thing and the routing can change completely and since you’ve got no constraints there is nothing to...
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    Closed: Re: buzzer and timer construction

    And then there's that talking Dutch pot cover...

    Sleep well.
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    Closed: Re: buzzer and timer construction

    What? WHAT???

    I understand the first part of your question; the second part, not at all.

    You could use a simple microprocessor to provide the counting and display functions.

    But, I don't...
  17. Closed: Re: Connect 32 serial lines to uC (eg. ESP32) over I2C or SPI?

    It’s sounding more and more like you should use an FPGA. What you’re proposing, daisy-chained uCs, 9bit UARTS, etc. just sounds like a nightmare to me, ESPECIALLY when you try to start debugging this...
  18. Closed: Re: Connect 32 serial lines to uC (eg. ESP32) over I2C or SPI?

    Well, maybe now is the perfect time to learn about FPGAs! There are megatons of information about FPGAs out there. Try one of the vendor sites (Xilinx, Altera(Intel), Lattice) for a starting point....
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    [SOLVED]Closed: Re: filtering a output of xor-ed signal

    Depending on your design, those glitches may not be a problem at all. Or they may. You don't tell us anything about your design other than there's an XOR in it.
  20. Closed: Re: Connect 32 serial lines to uC (eg. ESP32) over I2C or SPI?

    Either you need all 32 channels active at the same time, or you don't. You seem to be unsure about this. Personally, I'd probably just do this in an FPGA with 32 RS232->TTL converters. I'm not sure...
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    Closed: Re: Reduce Net delay in FPGA synthesis?

    Let me answer your question with a question: Your net delay is greater than your logic delay; so what? Does your design meet timing? If so, don't worry about it. You probably just have a long route...
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    [SOLVED]Closed: Re: filtering a output of xor-ed signal

    You have discovered the reason for using synchronous (clocked ) signals. When you have both signals transitioning simultaneously, there will be points in time where they are both interpreted as...
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    Closed: Re: Tramsit sound over UART

    A lot of undefined parameters... Do you want to stream sound in real-time or send sound files? What frequency range? How accurate? Compressed?
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    [SOLVED]Closed: Re: RF Detector circuit design

    How can you be both unfamiliar with circuit design and still able to design simple circuits? How do you know its working? Your picture of your physical layout alone tells us you're deluding yourself.
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    [SOLVED]Closed: Re: RF Detector circuit design

    Absurd. I cannot explain how it is working because I don't believe it IS working.
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