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  1. Replies
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    [SOLVED]Closed: Re: Verilog Interview Question

    Sorry about this one, I posted this question in a hurry without checking the width of a & b in code. As it's a phone interview, the question was just multiply a 9 bit register & a 8 bit register -...
  2. Replies
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    [SOLVED]Closed: Verilog Interview Question

    Hi,

    I was recently asked this question in a Logic Design/DV interview,

    Suppose you have the following, what should be the bit width of c,d,e ? The interviewer said that the answers of my d & e...
  3. Closed: Difference between the two coding styles for clock gating

    Hi all,

    I'm trying to clk gate a few registers for saving power & couldn't understand the following. Below is a snippet of what I've tried

    Method 1 : where i explicitly coarse & fine gater...
  4. Closed: Question regarding register renaming in modern processors

    I was reading a paper from MICRO which says the following :



    I understand the part where he says that TOMASULO is inefficient as it uses reservation station's ID till the instruction commits....
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    Closed: GPU Pipeline Architecture Basics

    After years of reading about CPU uArch, I want to start learning about GPU pipelines & unfortunately ARM infocenter isn't helpful in this case. So, any good recommendations as to where I can start to...
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    [SOLVED]Closed: ORing even & odd bits of a vector

    Suppose, I have a vector:

    logic [127:0] x; // one hot


    I want to OR the even bits & odd bits seperately, as in x_even = x[0] | x[2] | x[4] | ...... x[126] & similarly for the odd bits. I tried...
  7. [SOLVED]Closed: Reduction operator on a multi dimension vector

    Hi,

    I had a basic question, as in what would be the dimension of the o/p after performing a reduction operator on a multidimension vector ?

    Sippose I have a vector,

    logic [1:0] test [5:0];
    ...
  8. [SOLVED]Closed: Re: Verilog Code giving wrong output for subtraction / -1 * number

    I understood the error, there was a missing end .. statement. Not sure why it didn't raise an error
    always @(count,out2_complex_bf1,out2_real_bf1) begin

    if (count >= 4'b1000) begin
    ...
  9. [SOLVED]Closed: Any Shortcut for assigning msb of a product to a variable

    Hi,

    I am multiplying two variables (16 bit) in verilog, so the maximum number of bits of the product is 32 bits. Is there any shortcut to assign the msb 16 bits to a variable ?


    parameter a =...
  10. [SOLVED]Closed: Verilog Code giving wrong output for subtraction / -1 * number

    Hi,

    I am trying to do the following in Verilog: if count < 8, pass the i/p to o/p, else multiply the i/p by -j. Note: i/p is a complex number.

    My code:


    always...
  11. Closed: How to edit model file parameters from the spice file before running a simulation

    Hi,


    I have a spice file like this:


    **Test inverter
    .TEMP 110
    **Use high temperature to simulate worst case delay and leakage power
    .OPTION
  12. Replies
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    Closed: Re: Error in Delay Measurement ---- Spice

    1. Yes, the o/p waveforms are as they should be.
    2. I've removed TD = 10ns/ AT = 10ns, even then it gives same error.
  13. Replies
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    Closed: Re: Error in Delay Measurement ---- Spice

    I've tried this & this:


    .MEASURE TRAN tdlay TRIG Vout VAL = 0.5 AT = 10n RISE = LAST
    + TARG Vin VAL = 0.5 FALL = LAST

    .MEASURE TRAN tdlay TRIG Vout VAL = 0.5 TD = 10n RISE = LAST
    + TARG...
  14. Replies
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    1,234

    Closed: Error in Delay Measurement ---- Spice

    Hi,

    I'm trying to measure the delay in hspice for an inverter by using .measure command.


    **Test inverter
    .TEMP 110
    **Use high temperature to simulate worst case delay and leakage power ...
  15. Closed: Why does reducing frequency allow for downsizing of transisitors (Weste & Harris)

    Hi,

    I've recently started reading CMOS VLSI Design by Weste & Harris. While reading, I've found this statement " Reducing frequency allows for downsizing transistors/ using a lower supply voltage,...
  16. Closed: Detecting 3db power gain vhdl (using unsigned lib)

    Hi,

    I need to calculate 3db power gain. The file uses unsigned library & i cannot change/add signed library as the file is being used by others as well.

    I have the power values of the current...
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    Closed: Re: HDL Simulation in Modelsim from Matlab

    Yes i know about HDL Coder & Matlab Cosimulation.They are mostly used when you have matlab code & you want it convert it to HDL & quickly check simulation in modelsim.

    But my requirement was...
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    Closed: HDL Simulation in Modelsim from Matlab

    I have generated test cases in matlab.Now from MATLAB,itself i want to invoke modelsim & pass the .do file which has the tcl script to run the functional simulation..

    I'm doing this:


    tclstart...
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    1,726

    Closed: Re: Dell Laptops shut off

    Hi,

    I have a Dell Inspiron 15 Laptop(about 4 yrs old).I also faced a similar issue,that after powering it on it switches off within 1 min,sometimes it used to switch off before the windows lock...
  20. Closed: Re: Starting a counter by driving a register through UART

    Those syntax errors were only because i was directly writing the code here on website rather than in a suitable text editor.
    But i don't see much difference between what these two codes accomplish...
  21. Closed: Re: Starting a counter by driving a register through UART

    signal count : std_logic_vector(31 downto 0) := x"00000000";
    --
    --write high is the register into which UART will write number of pulses to store
    begin
    ...
  22. Closed: Starting a counter by driving a register through UART

    Hi,

    The subject title of this question came out a bit weird,so i'm going to explain my query -

    From UART i'm driving a 32 bit register(write_high).The register is the number of clock cycles i...
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    Closed: Re: uwire in system verilog

    In system verilog AFAIK we use :

    uwire for connections with a single driver.
    wire for connections with any number of drivers.
  24. Replies
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    Closed: Re: Bitlib library for VHDL

    I'm assuming you have a code which uses some packages compiled into Bitlib library & now you're searching for this library.

    A quick google search led me to a book on a university page which says...
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    Closed: Re: edge and center aligned data

    SDR - Single Data Rate (at single edge)
    DDR - Double Data Rate (at both positive & negative edge)

    119792
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