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Type: Posts; User: The_Dutchman

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  1. Replies
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    1,159

    Closed: Re: Coaxial cable capacitance

    Thank you all for giving me a more clear sight on how this works as I was confused with the capacitance stated in the datasheet, now it is more clear to me. I also looked up some video's on youtube...
  2. Replies
    8
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    1,159

    Closed: Re: Coaxial cable capacitance

    Hi Barry thanks for the reply. Yes I understand because of the voltage divider. But my concern is more the capacitance of the coaxial cable. At what speed will I be able to switch? Is this coaxial...
  3. Replies
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    1,159

    Closed: Coaxial cable capacitance

    Dear All,

    I'm planning on using a transistor to drive a 75 Ohm coaxial line (RG6) with just a digital signal. From collector to VDD there will be a 75 Ohm resistor. The signal at the collector is...
  4. Closed: Re: Input & output delay in mixed signal chip - RTL Signal Integrity

    Hi ~Sam,

    Thank you for your reply. On point 1 the input constraints, I'm not sure I understand how they are asynchronous. The inputs are 5 bits parallel. The modules I will be using are in the...
  5. Closed: Input & output delay in mixed signal chip - RTL Signal Integrity

    Hi everyone,

    I'm an analog designer performing my first mixed-signal chip now and I have some confusion about input and output delay constraints.
    Basically I have a 5-bit thermometer decoder now...
  6. Closed: Current Steering DAC output matching, what's the difference?

    Hello all,

    I was looking into current steering DAC's output matching, and I was a bit confused, why do they match like this?:

    150848

    And why not like this?

    150849
  7. Closed: Virtuoso Custom Inductor Connectivity Short Circuit

    Hello Everyone,

    I'm using a Virtuoso connectivity driven design flow. If I use inductors from the PDK, they appear as a symbol in my schematic with 3 terminals (+ - and bulk) and they also have...
  8. Closed: Re: ADS Sparam mini-circuits balun 4-port but s3p?

    Is it possible to elaborate on that? Maybe a reference or a paper so I can understand it?
    Any idea how can I get a wideband 12Ohm (balanced) to 50 Ohm (unbalanced) transformation?
  9. Closed: Re: ADS Sparam mini-circuits balun 4-port but s3p?

    Thank you for your reply, however I don't want to use it this way.
    I would like to do a 50Ohm to 12.5Ohm conversion, so is it also possible to add a ground at the secondary and have the differential...
  10. Closed: ADS Sparam mini-circuits balun 4-port but s3p?

    Hello all,

    I'm used to working with ADS a little bit, but I can't seem to understand to simulate the TCM4-452X+ wideband balun from mini-circuits.

    I downloaded the s3p-file from over here:...
  11. Closed: Wideband decoupling switching load (DC-GHz range)

    Hello all,

    For a wideband load I'm trying to design the power supply decoupling. The load pulls about 200mA DC current from my power supply with about 100mA of amplitude peak current at 3V supply....
  12. Replies
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    2,682

    [SOLVED]Closed: Re: Cadence simulation P1dB vs. frequency

    I managed to get it working using the hb simulation, and also using the pss simulation. Putting frf in the beat frequency was the right approach and put prf as sweep variable 1 and frf as sweep...
  13. Replies
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    2,682

    [SOLVED]Closed: Cadence simulation P1dB vs. frequency

    Hi all,

    For my design in Cadence I would like to simulate linearity over frequency. So far I had no succes. I'm using the ADEXL environment.
    I can successfully simulate the P1dB at a single...
  14. [SOLVED]Closed: Re: Layout hierarchy PIN connectivity issue

    You have to make sure to put the extract connectivity level high enough (>0) so connectivity is extracted to the lower hierarchical levels. This can be found under Options-> Layout XL-> Connectivity...
  15. [SOLVED]Closed: Layout hierarchy PIN connectivity issue

    Hello all,

    I have a connectivity issue in my layout hierarchy.
    For demonstration I've recreated the problem of my layout in a few pictures.

    The problem is with the connectivity of PIN's.
    If...
  16. [SOLVED]Closed: Re: Increasing NWELL size in layout - hierarchy

    Using a 4-terminal device and drawing the guard ring myself indeed solved the problem. However I had to add a floating substrate connection pin in the schematic for the LVS.
  17. [SOLVED]Closed: Increasing NWELL size in layout - hierarchy

    Hello all,

    For my specific problem I need to increase some PMOS NWELL sizes from the PDK transistors. In my simulations I always used 5 terminal PMOS (S G D B PSUB) devices.
    However in the...
  18. Replies
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    2,764

    [SOLVED]Closed: Re: Cadence analogLib port DC voltage

    It does assume 50 Ohm load matching, thanks!
  19. Replies
    3
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    2,764

    [SOLVED]Closed: Cadence analogLib port DC voltage

    Hello all,

    I've found a rather strange behaviour in Cadence Virtuoso which I cannot explain instantly.
    I use a port from the analogLib library to set a DC voltage. I then sweep this DC voltage...
  20. Replies
    0
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    4,122

    [SOLVED]Closed: Calibre DRC error exporting layout

    Hello all,

    I have a strange problem running DRC check using calibre. When I start Virtuoso, license "111" is succesfully checked out and everything works fine (Schematic, Layout, MMSIM).
    I...
  21. Closed: Wideband balanced impedance transformation

    Hello everybody,

    For my application I need wideband (10MHz-1.9GHz) impedance transformation (1:4), but I need it to be balanced input, balanced output. Could I use this kind of impedance...
  22. Replies
    3
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    1,227

    Closed: Oversampling / Skew compensation - VHDL

    Hello,

    For my master thesis I'm using a transceiver (fancy serializer) that has a 64-bit wide TXDATA input port that gets serialized from bit 0 to 63 on the rising edge of TXUSERCLK2.
    However...
  23. Replies
    1
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    1,282

    Closed: Two Stage Miller OTA gain?

    Hi,

    I am designing a 2-stage miller OTA like the one in the attachment.
    I need 72dB DC-gain, currently I'm stuck on 57.8dB.

    I've calculated an expression for the gain:
    Av(DC) =...
  24. [SOLVED]Closed: Cadence: How to give multiple instances different variables?

    Hello,

    I'm drawing a 2 stage fully differential miller OTA with 2 CMFB networks. These CMFB networks are ideal and contain a vcvs with a gain "Acm". However, when I put 2 instances on my schematic...
  25. Replies
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    1,222

    Closed: Simple SNR calculation S&H

    Hello,

    I'm designing a differential sample-and-hold. I have some specifications I have to met. The maximum supply voltage is 1.2V and there is chosen to be 100mV margins on the supply lines...
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