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Type: Posts; User: Chinmaye

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  1. Replies
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    1,189

    Closed: Computing exponential in verilog

    Dear all,

    I have been trying to use exponential function in verilog. I want to calculate an expression like below.
    Let x = 3.987
    x^6 + x^8- x^5 = 10.

    How can this be done in verilog?
    TIA
  2. Replies
    11
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    1,189

    Closed: Re: Solve Equations Verilog

    So i basically start with an initial guess for variable 'a'. Then i try to compute the equation substituting my initial guess for 'a'. The problem is, 'a' can take a decimal value. As in, if a =...
  3. Replies
    11
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    1,189

    Closed: Solve Equations Verilog

    Dear all,
    I am trying to solve equation of a^7-2a^5-a^2 = -1. How can one implement this in verilog with minimum hardware?
    TIA
  4. Closed: Calculate the INL of ADC using inl function in calculator in cadence

    Dear all,
    I am trying to use INL functionality in cadence virtuoso calculator for the calculation of INL of the ADC. When i give the following input "inl(v("/OUT_DAC" ?result "tran") 0.001 ?mode...
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    263

    Closed: Error in AMS simulation.

    Dear all,
    I have verilog block for which i have created symbol. I tried to test only that block performing AMS simulation and it works. Now i try to put it the actual design and perform AMS...
  6. Closed: Re: Converting verilog code into a symbol during AMS simulation

    Thanks for the help,
    So i split the inputs while defining input output pins in the module. For example
    module inve(in[1], in[2], out[2], out[1]);
    This seems to work
  7. Closed: Re: Converting verilog code into a symbol during AMS simulation

    How will i be able to split the pins? As in, I would like to have 4 pins by name in[0], in[1], in[2], in[3] instead of one pin in[3:0].
  8. Closed: Converting verilog code into a symbol during AMS simulation

    Dear all,
    I have a verilog code with input in[3:0] and output out[3:0]. When i try to create a symbol for it for ams simulation, it gives me only 2 pins. One pin for input, in<3:0> instead of 4 pins...
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    2
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    328

    [SOLVED]Closed: AMS simulation of D-FF

    Hello all,
    I am unable to simulate D-flipflop properly in AMS. The input that i am giving is itself shown incorrect on the wave form window. I was able to simulate simple gates but find ing problems...
  10. Closed: ConnectLib files in ams simulation Cadence

    Hello all,
    I am trying to perform a test AMS simulation. After ADE launch, we go to setup->Connect rules. There i see a set of standard rules like 18_full_fast, 5_full_fast etc. All of these have...
  11. Replies
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    368

    Closed: Combine circuit and Verilog in Cadence

    Dear all,
    I have an ADC design in cadence virtuoso which is at transistor level. I would like to perform some operations on this output of the ADC. Is there anyway that i can write a verilog code...
  12. Closed: Re: Verilog-a code for differential amplifier

    Thank you. Shall try this.
  13. Replies
    7
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    573

    Closed: Re: Verilog-a code to latch analog voltages

    @cross() does not allow V() inside it. Hence it cannot be used
  14. Closed: Re: Verilog-a code for differential amplifier

    CMOS switch
  15. Closed: Verilog-a code for differential amplifier

    Hello all,
    Here is a simple verilog-a code for an amplifier with differential input and differential output. This works fine with resistors but if i try to use it with switched capacitor circuit, it...
  16. Replies
    7
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    573

    Closed: Verilog-a code to latch analog voltages

    Dear all,
    I am trying to model analog latch in verilog-a but have been unable to do it. The requirement is as follows
    It is required to sample an analog value at positive clock cycle of CLK2 and...
  17. Replies
    1
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    268

    Closed: Generate pulses of different widths

    Hello all,
    I would like to generate pulses of different widths at different instances of time in cadence virtuoso. How can it be done?
  18. Replies
    1
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    348

    Closed: Warnings in nano route in innovus

    Hello All,
    I get this warnings while Nano Route. Due to these warnings, routing is not happening. Any idea how they can be resolved?

    #WARNING (NRDB-2040) Rule LEF_DEFAULT doesn't specify any...
  19. Closed: ramp generation using switched cap integrator

    Hello all,
    I am generating a ramp from 0 to 1V with 10mV steps using a differential switched cap integrator. But my requirement is to generate a ramp from -0.1V to 0.9V. How will I be able to...
  20. Closed: Re: Convert ITF file to ict for captable generation

    Sir, What is a linux binary file? Could you please explain more on this? Also is it possible to create layouts in innovus, without using captable files?
  21. Closed: Re: Convert ITF file to ict for captable generation

    How does the utility look like? Does it have any extension?
  22. Closed: Convert ITF file to ict for captable generation

    Dear all,
    I want to convert itf file to ict file and use it for captabl generation. How can it be done?
    The following link provides commands to do it. But again i do not understand that....
  23. Replies
    2
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    307

    Closed: Very accurate analog comparators

    Any leads on how to go about building an analog comparator that can detect signals even with 20mV difference?
  24. Replies
    7
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    675

    Closed: Re: Saving the layout in innovus

    Thank you sir. I was able to generate the gds file using the command stream out. But when i use the same .gds file to generate layout in virtuoso, there are lots of missing layers and it looks...
  25. Closed: Re: what is the bandwidth achieved for the given configurations

    For s single stage, Gain * Bandwidth product is constant. Gain of triple cascode >cascode > common source. Hence Bandwidth of Common source > cascode> triple cascode
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