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Type: Posts; User: dick_freebird

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  1. Replies
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    172

    [SOLVED]Closed: Re: Resistors in Wilson current mirror

    They improve Vbe-match and current-match fidelity (if
    the resistors have better matching tolerance than the
    transistors' Vbe). You need to establish a current across
    the resistors which dwarfs the...
  2. Replies
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    Closed: Re: inverter Vhigh reduced

    Probably an ASIC test chip.

    50 ohms is definitely going to challenge even a high
    drive logic buffer. If you had (say) a "10mA" buffer for
    1.2V rated at 90% Vdd that says 120mV/10mA=12ohms
    and...
  3. Closed: Re: [moved] Value of lateral electric field(E0) in UMC 65 technology

    If you're talking the true lateral electric field, that's just Vds/Leff.
    But at the drain, the gate-drain field is also an element of hot
    carrier generation / steering / degradation (canonical...
  4. Closed: Re: "RS-232 port to transfer data to PC for analysis"

    "Back in the day" (like, '60s through '90s) RS-232 was
    the most common PC interface (other than printer
    port).

    If you have no RS-232 port there are USB-serial
    dongles that will do the job....
  5. Closed: Re: PCB design 450 MHz LVDS trace routing

    100 ohms differential is the same as two 50-ohm-to-
    common-mode-point impedances, and no conductance
    to the ground plane (provided that balance is good and
    skew is nil). Maybe 50-ohm high...
  6. Closed: Re: NPN having its VBE protected against reverse voltage....but unecessary?

    https://www.google.com/search?q=NPN+%22hot+carrier%22

    Most detailed papers are copyrighted but persons unconcerned
    about this can find interesting yet accessible papers amid the
    pay-wall hits....
  7. Closed: Re: "Current" controle is a big issue using ClassD ?

    Current mode control IME is about load-step response.
    Class D doesn't have load steps per se, only as much as
    output voltage dictates against the fixed(ish) load.

    What benefit does anyone claim...
  8. Closed: Re: NPN having its VBE protected against reverse voltage....but unecessary?

    The point of relative areas is semi-irrelevant. Inducing non-active
    (usually) regions to "steal" base current from the region that
    actually has current gain ruins low current beta, and...
  9. Closed: Re: NPN having its VBE protected against reverse voltage....but unecessary?

    The entire surface must be insulated. Consider the usual
    vertical NPN. To get to the emitter, the centermost active
    region, you must traverse isolation, collector and base.
    If the surface were not...
  10. Closed: Re: NPN having its VBE protected against reverse voltage....but unecessary?

    BJTs still have the "field oxide" insulating the metallization
    from silicon. CMOS adds the engineered thin oxide (active
    area) as the gate insulator, a field oxide etch followed by
    controlled...
  11. Closed: Re: Difference between NMOS/PMOS with and without Deep Nwell

    If deep nwell is -only- deep and does not abut the
    surface, then it can isolate a P pocket for NMOS which
    is no different than the plain epi / bulk. There would be
    a regular NWell for PMOS which...
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    Closed: Re: Is it a transistor or a mosfet?

    I would be inclined to think that this is an overvoltage
    warning light and if true, then I would pick a PNP BJT
    for the function with emitter to the LT1057, base to
    the resistor/zener/resistor...
  13. Closed: Re: NPN having its VBE protected against reverse voltage....but unecessary?

    Pushing carriers acros the reverse breakdown potential makes
    them "hot" electrically and they can leave the silicon and embed
    holes or electrons in adjacent oxides.

    This charging changes surface...
  14. Closed: Re: Will we get tombstoning of this capacitor and resistor?

    I don't know about your SMT assembly process (that's who
    ought to be asked, because there's probably a good bit of
    specifics involved) but I can tell you that capacitor lands
    that are fully part...
  15. Closed: Re: NPN having its VBE protected against reverse voltage....but unecessary?

    The case where load is energized and then power is discharged
    could apply damaging reverse bias to the NPN.

    Low current reverse breakdown may only drift Vbe and cost low
    current beta - hot...
  16. Closed: Re: Modelling power supply for cadence simulations

    What do you know about the characteristics of your chip's
    "power take"?

    Modeling a CMOS op amp would be very different interests
    than a POL DC-DC, than a RFIC, than an ADC. Each has ...
  17. Closed: Re: Adding capacitor to Cgs in low side FET of sync Buck converter.

    If this were the only interest, then perhaps. But it never
    is, is it?

    Adding passive Cgs adds switching loss without improving
    conduction loss. Adding enough to matter, may drive you
    (heh) to a...
  18. [SOLVED]Closed: Re: Legality of use of internet sourced out-of-print application notes and data books

    Don't overthink it. Nobody cares about your purity when
    the subject is out-of-print materials that you're only
    reading, that were published freely originally.

    Copyright pertains to selling....
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    Closed: Re: MOSFET soi, to use LTSpice

    LTSpice is meant for IC applications support and the MOSFET
    models they provide are meant for the discrete transistors
    such applications would want. Low voltage SOI CMOS is not
    that. So Linear...
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    Closed: Re: Reference for VCO and PLL

    Somewhere, someone has to provide a "golden" frequency
    standard. At test you would use the test equipment set's
    master 10MHz most likely, as everything else is slaved to
    that. Though maybe...
  21. [SOLVED]Closed: Re: Protect FPGA Pin from negative voltage

    You do not want to be in a "diode vs diode foot race" thinking
    you're going to prevent latchup. Differences between chip and
    diode junction temp, or just a bit too much overshoot
    (undershoot)...
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    Closed: Re: Polarization MOSFET SOI

    Applied voltage varies with technology and application environment.
    Ground (or negative rail) is common, but SOI technologies meant for
    space and other radiation environments may apply a more...
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    Closed: Re: Polarization MOSFET SOI

    P- to intrinsic, depending on the desired VT. Either a
    desirable starting material doping, or VT adjust implants.
  24. Closed: Re: Data Transfer over long rwisted pair cable

    The RS-422 / RS-485 cable plant has a bit rate * distance
    product in the specs. Whether you can "overclock" it is
    going to depend on intersymbol interference, probably
    not pretty.

    What...
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    Closed: Re: Induction Cooktop Circuit Design

    That ought to do, especially if the pipe is also earthed.
    Probably wants some attention to durability of the
    insulation against various fault scenarios like water
    intrusion, gross...
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