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Type: Posts; User: barry

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    Closed: Re: Vivado Timing Constraint

    At the risk of stating the obvious : It’s a timing constraint. In Vivado. It tells the tools how fast the FPGA has to run. As far as I know there’s nothing explicitly called a “Vivado timing...
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    Closed: Re: Not enough IOB of a certain FPGA

    Um, maybe pick an FPGA that has at least 512 IOB?
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    Closed: Re: pulse width stretching

    Are you designing a chip? That would have helped if you mentioned it 50 posts ago.
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    Closed: Re: pulse width stretching

    Cant you use a spice model?
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    Closed: Re: pulse width stretching

    Isn't a Schmitt trigger AND gate a digital gate?
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    Closed: Re: pulse width stretching

    I still dont know what you mean by "realizing". What is your simulator?
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    Closed: Re: pulse width stretching

    I'm not sure what you're asking.
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    Closed: Re: pulse width stretching

    You need to do some actual engineering here. Here's what you need to think about:

    If you use the circuit I showed in post #12 you need to ensure that the input pulse is wide enough (low) to...
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    Closed: Re: pulse width stretching

    So you're going to need to put a diode across the R so that the cap charges fast.
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    Closed: Re: pulse width stretching

    What’s the duty cycle? If you have 500 ns pulses with a 50% duty cycle, there won’t be time for the cap to charge (as has been pointed out). And what’s the stretch-time? In order to do a proper...
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    Closed: Re: pulse width stretching

    Is this what you want, or not? If it is, my original suggestion does exactly this. I think it’s time now for you to provide more specifics of exactly what you want. Min/max input pulse width, output...
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    Closed: Re: pulse width stretching

    Just use a single ST AND, e.g., 74HC7001, or two NANDs. No reason to use two packages.
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    Closed: Re: pulse width stretching

    It's a bad idea because you'll never pull the input lower than one diode drop+Vlo of the source. This may not be low enough to effect a logic '0'.
    .
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    Closed: Re: pulse width stretching

    Bad idea. Use this:

    153653

    Have to consider pulse width, etc. in selecting RC. Can also put diode across R for narrow input pulse.
  15. Closed: Re: Find dc voltage gain and phase margin from graph

    You do not need to see where phase crosses -180 degrees; you just need to see where gain crosses zero. The phase margin by definition is the difference of the phase at 0dB and -180 degrees.
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    Closed: Re: pulse width stretching

    I don't think there are any one-input AND gates.
  17. Closed: Re: Find dc voltage gain and phase margin from graph

    DC gain is, um, the gain at DC, i.e., zero frequency.

    There is no way to determine phase margin from your graph.
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    Closed: Re: pulse width stretching

    Could you give us more information? Is this a digital system? Is there a clock? You could use a schmitt-trigger AND gate where the signal goes directly to one input and through an RC to the other...
  19. Closed: Re: Speakers make a loud noise when turning off. Is there a way I can eliminate it?

    Why do you keep on insisting that with your admitted limited knowledge of electronics that you are going to "fix" this? We've already established that the problem is in the design, not a defective...
  20. Closed: Re: Speakers make a loud noise when turning off. Is there a way I can eliminate it?

    The manufacturer has already said this is normal operation. There is no “problem” other than, perhaps, a bad design. Checking caps and diodes is a fool’s errand. It most definitely has something to...
  21. Closed: Re: Speakers make a loud noise when turning off. Is there a way I can eliminate it?

    I think you already have your answer. Unless you:

    1) Redesign the amp, or
    2) Buy a different speaker

    you are going to have to live with this.
  22. Closed: Re: Ethernet vs USB discussion and/or comparison

    You're comparing apples and doorknobs. Although you could use either for certain situations, there are profound differences. Ethernet is intended for networking multiple computers; USB is intended to...
  23. [SOLVED]Closed: Re: Please help me this code which 64 QAM MATLAB CODE.

    The error is that you posted an arcane block of code with no explanation of what it’s supposed to do, what your problem is, or ANYTHING useful, and then you expect us to “find the error”.
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    Closed: Re: Using a potentiometer to measure arcseconds.

    There’s no optical encoder that will come close to the OP’s requirement. Probably the best you will find is 65536 counts/ rev. And even that is going to be expensive.
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    Closed: Re: Active-HDL VHDL simulation problem

    What about a_i and b_i? If they’re unconnected c_out will be undefined. Show ALL your signals. There’s probably a problem with your elaboration
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