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Type: Posts; User: tarkyss

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    Closed: How PA/PTPX handle analog macro

    analog power calculation is different with digital, how PA/PTPX handle analog macro? calculate according with lib file? the lib file of analog is different with digital?
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    Closed: Re: A Debussy question about lib

    you must compile the library at first, and then specify the library in the denali rc file
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    Closed: A question about function coverage report

    I have a question about function coverage report
    I defined function coverage, and generated simv.vdb/fcov directory too, the result.db is 17k, so I think the function coverage is generated
    but...
  4. Closed: One question on PCIe

    I am not sure the function number in the PCIe packing
    I want to design a chip with an PCIe interface, there are several module in the chip, these modules may access PCIe, so I think I can assign an...
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    Closed: A question on coverage merge

    I use nc-sim to verify our design,
    when I merge lots of coverage test results, an error occurred
    "failed due to mismatch in design checksum with the loaded model file"
    the reason maybe the dut...
  6. Closed: search for SRAM

    I want to find a SRAM, which can support burst read/write
    It'd better has a last burst input signal, which means the last symbols when burst transactions.
    any suggestion?

    if a rom can support...
  7. Closed: Denali question

    ljxpjpjljx, do you know how to preload mem for denali model? thanks
  8. Closed: denalimemtransaction

    In order to verify reading mem operation,
    data prepared in mem with setData function of DenaliMemTransaction class
    for example, trans is an instance of DenaliMemTransaction, data1 and data2 are ...
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    Closed: Doubt about two technologies..

    I think it is possible there are 65nm transistors and 90nm transistors in a sigle chip, but that doesn't mean two technologies.
    and I realy don't know two different technologies can be in a chip,...
  10. Closed: specify in verilog

    I am not sure I understand your question correctly
    I think there are several ways to solve it, for example
    1, specify delay in your RTL code, which is only for behavior simulation, while set...
  11. Closed: Re: Setup and Hold violation for the same register?

    if the input of the ff is a asynchronism signal, it is possible.
    for synchronous signal, the same path, I don't think so,
    but the input of the ff may come from several different source, for example...
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    Closed: astro spice netlist

    you can extract spf netlist with star-rcxt, which can be read by spice
    hercules can do it too
    by the way, the RC extract by Astro is not done by itself, it call star-rcxt to do that
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    Closed: Looking for a Jop in China(ASIC)

    I am working in Japan now, but I want to go back to China
    I have four years experience in ASIC digital front end and three yaars in back end
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    Closed: some questiones about LDPC

    thank you, muralicrl.
    but I have the documents you pasted,
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    Closed: some questiones about LDPC

    How many bits can be corrected when LDPC decoding at most?
    Actually, my question is how many bits can be changed when LDPC decoding at most, including the case of decode error.
    It can be...
  16. Closed: a synthesis problem

    thanks, i think i have solved it yet
  17. Closed: How can I add constraint for clk2 and data1 when I synthesis my block?

    there are one clk1 in my block,
    clk2,data1 are generated in clk1,
    while clk2 is not used in my block, it is used by another clock,
    and the block will capture data1 by clk2,
    how can i add...
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    Closed: 3 questions in SOC Encounter, pls help me!!

    SOC Encounter only support FE-TCL? I am not sure
    if it is true, there are lots methods to solve it.
    for example, you can read your design with virtuso, and then do it in virtuso.
    or read your gds2...
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    Closed: Re: 3 questions in SOC Encounter, pls help me!!

    for cadence tool
    skill is the best language
    you can write a skill script to solve the first and the second problem
    it is not diffcult
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    Closed: Library Design Flow

    I designed a standard cell library and IO library several years ago,
    firstly, you should know which cells you want added into your library, and determine some parameter, for example, cell height,...
  21. Closed: cdc_wp.pdf

    can I transfer data between two clock domains like that?
    I think it is dangerous, because the bits of the data may delay one cycle or two cycles, so some bit may be the current data, and some may be...
  22. Closed: debussy tool

    you can specified the file with inlcude command in your verilog
    and then compile the verilog file with vericom
  23. Closed: Re: VDSM issues

    Signal-integrity, noise, process variation, over-the-cell routing and metal migration.....
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    Closed: DFM

    DFM is Design for Manufacturability
    Design for Manufacturability includes a set of techniques to modify the design of integrated circuits (IC) in order to make them more manufacturable, i.e., to...
  25. Closed: skill language

    Yes, skill is script language of cadence, if you use IC, i think you had better learn it, what it can do is more than the menu command
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