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  1. Closed: Re: FYP ideas suggestion on FPGA, or FPGA based network processing/network on chip

    How about a Zynq design that randomly searches websites and finds a FYP title for someone
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    Closed: Re: Multiplexer output width depends on SELECT

    The second case I wrote above is not a mux I just use that type of syntax to improve the readability of the code instead of having a bunch of if statements

    in_slice1 is not the same as the other...
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    Closed: Re: Multiplexer output width depends on SELECT

    Not the way you seem to want to implement it as auto resizing hardware during operation.

    If you mux the largest bus width and slice only the bits you need that can be done. e.g.

    parameter...
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    Closed: Re: Multiplexer output width depends on SELECT

    What you are doing is something that can't be done in hardware.
    You can't have hardware that magically adds or deletes chips on a board to make buses that change widths on the fly.

    You implement...
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    Closed: Re: I2C not working properly

    The second picture in post #13 isn't how you measure the delay between the falling edge of the SCL and the SDA.

    My bet is that the signals you think meet the 300 ns (internal required hold time)...
  6. Closed: Re: Using calculated CRC as seed for the next CRC calculation

    You do understand that a CRC has a feedback that uses whatever is already there to compute the next CRC of the input data. This is why you have to INITIALIZE the CRC to all 1's normally at the start...
  7. Closed: Re: [moved] VHDL of input capture and output compare

    ASIC world has a bunch of examples of various blocks that are used to create larger designs.
    http://www.asic-world.com/examples/vhdl/index.html

    If you can't translate from the blocks in your...
  8. Closed: Re: [moved] VHDL of input capture and output compare

    You question isn't clear.
    What do you mean by input capture and output compare?

    If you already have an architecture diagram post it so we have an idea what you are trying to do.

    If you just...
  9. Closed: Re: Facing some error in Verilog HDL coding of Standard deviation calculation?

    Yes, I saw those errors, but can't comment on them as post #3 noted the source is outside the project.

    Look at your source and see why the things like the range are not constant.

    Like I said...
  10. Closed: Re: Facing some error in Verilog HDL coding of Standard deviation calculation?

    Did you look at the xvlog.log file that the error suggests you look at?

    It seems to indicate you've written your code incorrectly.

    My guess would be you tried to write a software like...
  11. Closed: Re: Unable to run the simulation correctly ( Modelsim )

    Please use code tags from now on I don't like having to download files to read code.

    This is probably not synthesizable code or will synthesize to something that doesn't work like you expect....
  12. Closed: Re: Implementation of a MUX for selecting from 2 different sets of inputs

    You really need to learn how to ask a question and describe exactly what you are trying to accomplish. Writing a bunch of vague descriptive text makes it extraordinarily difficult to understand your...
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    Closed: Re: CDC - How make merge data after conversion?

    You're reading at 2.4x of the write rate, so the FIFO goes nearly empty. Apparently you are stopping the reading at the 2.4x rate when almost empty, and restarting at programmable full. During that...
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    Closed: Re: I2C not working properly

    This along with a previous post that suggests smaller pullup resistors improves things seems to indicate that the rise time of the signal with added noise (don't know your setup with driving the SCL...
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    Closed: Re: I2C not working properly

    How is the reset to the IP core handled? One big difference between ASIC and FPGA is both Altera and Xilinx both have flip-flops that power up in a know state. ASICs flip-flops won't necessarily...
  16. Closed: Re: Digital Storage Oscilloscope - newbie questions

    The screen shot utility of the scope is suspect as they are not in persistence mode and the scope appears to be in continuous mode so, I would think the scope would only show a single trace not...
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    Closed: Re: HELP ME the newbie with Verilog Code

    I would venture to say you aren't even making an effort.

    I did a quick search for "Verilog digital clock code" and it came back with 628,000 results and the first 5 links have Verilog code to do...
  18. Closed: Re: Digital Storage Oscilloscope - newbie questions

    The display is "normal" if you have a persistence mode enabled, which will continue to show previous traces that were generated.
  19. Thread: "Closed" thread

    by ads-ee
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    Closed: Re: "Closed" thread

    Settings (upper right next to logout) -> my account (left panel) -> General settings -> Default thread subscription mode.
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    Closed: Re: BP4836 BMW Reverse RDS

    You would still need an entirely new interface board just to get the new radio to communicate with the front panel of the old radio I'm sure the new radio would have a ribbon cable that has entirely...
  21. Thread: "Closed" thread

    by ads-ee
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    Closed: Re: "Closed" thread

    I also don't see this behaviour.

    Just guessing, but have you tried clearing all the edaboard cookies while logged out? Can't hurt anything to try this and see if it corrects the problem.
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    Closed: Re: Switching between more bit-streams on FPGA

    I'm not sure exactly what you are asking.

    Partial reconfiguration has both a full configuration bitstream and one or more partial bitstreams that can reconfigure a isolated portion of the design,...
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    Closed: Re: SystemVerilog Input generation

    All you keep doing is telling us in text what you are doing. What you are doing is obviously wrong. It is the implementation details of your described testbench code that is at fault. Without the...
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    Closed: Re: SystemVerilog Input generation

    This doesn't make it simple. Word descriptions are not the simplest way to get a fix for something like this, which might be an issue with your understanding of Systemverilog or of how the simulator...
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    Closed: Re: SystemVerilog Input generation

    Without code or even a diagram of the structure of your testbench it is nearly impossible to tell you what is wrong.

    Based on the limited information in this post. If a counter has a clock it will...
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