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Type: Posts; User: andy2000a

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  1. Replies
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    Closed: Re: porting windows software to Linux OS

    crossOver look like commerical version wine .
    why porting windows OS to linux

    because someone test windows OS is poor
    just like hspice run on windows OS
    will slow than linux in the same case...
  2. Closed: synopsys solvnet password

    goto china eda forum

    LIKE HERE
    http://www.eetop.cn/bbs/forum-47-1.html

    someone will upload tool , but very very large
    and hard to download ..
  3. Closed: Re: FREEWARE Layout Editor

    use wine + layout.exe

    look like response is slow
  4. Closed: FREEWARE Layout Editor

    Layout Editor

    http://www.batelab.com/software/
    winXP version only support GDS-II

    and will have ubuntu & linux OS version
  5. Replies
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    [SOLVED] Re: Leakage measurement using Hspice

    hspice or synopsys some tool ,
    as I remember have other tool like hsimplus or others ..

    can use script file to monitor leakage current

    Vgs Id ..etc
  6. Replies
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    Closed: porting windows software to Linux OS

    linux os have some tool called wine www.winehq.org .some small eda can be run under linux OS

    like red hat 8

    use wine can use spice exploer windows version
    or psim

    but large tool is fail...
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    Closed: install wine on centos 5

    wine can run some windows program

    some windows eda also can be run under wine
  8. Closed: schematic to verilog code

    verilog -> logic synthesis -> verilog in (cadence tool )

    or use debussy but not synthesis
  9. Closed: Re: Isolation between analog and digital power lines

    analog & digital in the same substrate . sometime noise couple from SUB

    even use guard ring ..

    use "away from "
  10. Closed: Power DMOS Layout

    High volt model L49 not accurny

    maybe you can use Level66 88 or 101
  11. Closed: Re: virtual machine

    vmware release thinApp (ger this product from inthInstall Corp)

    ThinApp package some DLL .. and make Execute software .

    but some tool maybe need license file
    can be package to signle file...
  12. Closed: Synthesis Tool

    As I know PC (windows Base) only

    SYnopsys DC 2000 --> but only beta test , and many bug

    Synplify ASIC
    Examplar
  13. Replies
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    Closed: Re: subsitute tanner software

    tanner is PC windows base EDA software .

    as I remember , PC base

    only Tanner Ledit
    mycad mychip
    Magice
    and some textBook have LASI( I am not sure)

    LASI is free layout
  14. Closed: Dolphin smash help!!

    Hi neils_arm_strong

    I ever use smash (2003?) simulation the same circuit with hspice

    smash Vs hspice , both use Level49 model
    and smash can simulation . Like amplifier AC simulation gain is...
  15. Closed: Dolphin smash help!!

    as I remember , dolphin smash simulation stimulate script is some different with hspice , but very close
    and maybe you need use smash stimulate

    like
    hspice time_step 10ns
    .tran 10n 1u
    ...
  16. Replies
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    Closed: I need TSMC 0.18m tech files

    above URL link is Tsmc spice model (for spice simulation) and GDS file , but Tech file
    include some setting , like Tanner tdb file
    design rule /drc/ LVS ..etc
  17. Replies
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    Closed: download tanner tools

    as I remember , in Linux eda enviroment (RHEL) , we usually use Laker /Virtuso ., we never use Windows base layout tool , Tanner can be use just for small company or student ,

    many foundry...
  18. Closed: Re: NeoCell

    where can i get neocell ??

    it be include in ic5.141 ?? or not ??
  19. Replies
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    Closed: l-edit

    Tanner v13 support 3D layout extract ..

    but SPR still use EDIF
    no verilog netlist input Place& routing
  20. Replies
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    Closed: a LDO quesiton,can someone explain?

    how about internal resgulator inside IC chips ? many IC have multi inside power , but can not use large Cap .. in cmos process use opa + Pmos
    will cause system unstable ..
  21. Closed: Single Electron Transistor can be simulation by spice ?

    Single Electron Transistor is need device element
    which tool can simulation it ?
  22. Closed: Single Electron Transistor can be use in analog design or no

    Single Electron Transistor very very small ..

    It can be use in analog design in deep submicro or just only for digital circuit ?
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    Closed: which hv mos model will be use ??

    http://www.geia.org/index.asp?bid=597

    CMC - Compact Model Council

    The Compact Model Council was formed in August, 1996, for the purpose of promoting standardization in the use and...
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    Closed: comparator design

    we usually design OPA and need simulation gain_margin , phase margin ..
    for make sure our OPA can really work ..

    how about 2 stage comparator ?
    in gernel , we design a cmos comparator remove...
  25. Closed: who use smartspice or eldo in analog deisgn

    I ever use hsim/aditspice (nanosim powermill ..)

    smartspice is Spice engine tool , hsim maybe run fast , but some analog circuit like PLL or include inductor circuit , hsim have wrong simulation...
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