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Type: Posts; User: noureddine-as

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  1. [SOLVED]Closed: Re: SDF file backannotation problem: "Instance X does not have a generic named Y"

    Using Verilog behavioural libraries (instead of VITAL VHDL stuff) along with Verilog output Netlist resolves the problem.
  2. Closed: How to compile VCS simulator (simv) statically? and how to increase performance?

    Hi,

    I migrated recenly from ModelSim to VCS for performance issues (ModelSim was sooo slow for gate-level simulation plus I always had to generate VCD or FSDB and then feed that to PrimeTime which...
  3. [SOLVED]Closed: Re: How to trace the original of netlist gates back to the original RTL description

    No, what I mean is that, In the IP (which is actually a floating-point unit) there are a lot of arithmetic stuff .. and it's all combinational. So when it's synthesized you no longer no what comes...
  4. [SOLVED]Closed: Re: Looking for Synopsys documentation on their outputs formats used in PrimeTimePX

    In addition to what kungchuking and ThisIsNotSam said, you can export the power waveform as FSDB, and then open it using Verdi. There is an option to export in CSV format.

    I did that a long time...
  5. [SOLVED]Closed: Re: How to trace the original of netlist gates back to the original RTL description

    Okay ThisIsNotSam, that's what I do for know. The problem I had is with the leaf cells generated from the assign statements and muxes and stuff like that.
    I'm working this around by isolating each...
  6. [SOLVED]Closed: How to trace the original of netlist gates back to the original RTL description

    When an RTL circuit is synthesized for an ASIC technology, is to possible to trace back the original source code of the generate netlist gates?

    More specifically, I compiled an RTL IP using Design...
  7. [SOLVED]Closed: SDF file backannotation problem: "Instance X does not have a generic named Y"

    After synthesizing a SystemVerilog IP in Design Compiler 2019, I exported the SDF timing backannotation file to be used in VSIM for post-synthesis simulation.

    However, VSIM outputs a lots of...
  8. [SOLVED]Closed: Re: How to evaluate the energy of an arithmetic operation

    Thank you for you answers!
    I actually came across something that could simplify things (since I actually have a few dozens of instructions, so running each benchmark alone will take a hell lot of...
  9. [SOLVED]Closed: How to evaluate the energy of an arithmetic operation

    Hi,

    I have an ALU described in SV, with the corresponding Testbench that takes some input vectors, feeds them into the ALU, gets the result and then compares with the expected result.

    The...
  10. [SOLVED]Closed: Re: How to automate the maximum frequency estimation

    Thank you very much for these insights. Although it will still be manual for me, at least I have some tricks to speed things a little bit. Thanks all!
  11. [SOLVED]Closed: How to automate the maximum frequency estimation

    I am using Design Compiler to synthesize a set of circuits. The goal is to find for each circuit the Maximum frequency and the corresponding Area.

    Normally for a single circuit I would set an...
  12. Closed: PrimeTime provides different Power analysis results for FSDB vs. VCD files

    Hello,

    I'm trying to evaluate the power consumption of an FPU. I synthesized the IP for 350nm technology node using Synopsys Design Compiler. Then performed a post-synthesis simulation on ModelSim...
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