Type: Posts; User: vyella1

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  1. Replies

    Closed: Post synthesis gate level simulation

    Hello Forum,
    I am working on gate level simulations for generating saif file for power estimation. I am running simulations on post ICC generated netlist and sdf file(generated from prime time...
  2. Closed: Re: ASIC datapath design: Back-pressure (Stall) mechanism

    You can either do back pressure to all the pipeline stages, or instead send a signal from the fifo to the source(suppose say ab) of first pipeline stage saying not to send the data. From that source...
  3. Closed: Re: ASIC datapath design: Back-pressure (Stall) mechanism

    Suppose say you have 6 pipeline stages and a fifo after that. When the write pointer in the fifo points to FIFO_DEPTH-6-1, you can send a signal to the source of the data to the first pipeline stage...
  4. [SOLVED]Closed: Re: Design not simulating for different technology node

    Hello ThisIsNotSam,
    I synthesized the design at 600Mhz for 28nm technology and 400Mhz for 40nm technology. My testbench runs at 100Mhz. I am not using the SDF files. Instead I am using unit...
  5. [SOLVED]Closed: Design not simulating for different technology node

    Hello Forum,
    I did post synthesis simulation on netlist generated for two different technology nodes(28nm & 40nm) for the same design. The post synthesis netlist simulation worked for 28nm...
  6. Replies

    Closed: max_transition Violation

    Hello Forum,
    I work on front end synthesis of the design using design compiler topographical. After synthesis, there are no timing violations. But I am seeing "max_transition" violation. Is it...
  7. Replies

    Closed: Re: power analysis using synopsys DC compiler

    You need to run post synthesis simulation on the synthesized netlist and generate saif file first. Later load the synthesized design and libraries and give generated saif file as an input to design...
  8. Closed: Re: Output

    The synthesis tool will usually ignore is_x and will give it as a warning.
  9. Replies

    Closed: Re: Design compiler synthesis

    Thank you for responding Really, I am not Sam.
    Even I thought the same and I checked the log file, the retiming option is not turned on
  10. Replies

    Closed: Design compiler synthesis

    Hello Forum,
    I am working on RTL synthesis of an ECC Decoder(which has many sub modules) using design compiler, and I encountered a timing violation and the critical path is in sub module ABC....
  11. Replies

    [SOLVED]Closed: Code coverage of a design

    Hello forum,
    I am investigating on code coverage. I have a design and upon doing coverage analysis, the coverage report shows that my test bench does 70% of code coverage. Is it necessary to have...
  12. Replies

    Closed: synthesizing memory as latches

    Hi all,
    I am designing a decoder and my design uses memory. For some of the memory blocks I am using compiled memories and for other memory blocks I am synthesizing it as flipflops(synthesizing...
  13. [SOLVED]Closed: didn't find inverter for specified operating conditions

    Hi Forum,
    I ran a synthesis using design compiler for a using standard cell library which has operating conditions(Voltage=1.05V, Temp=25C). Now I want to run synthesis for different operating...
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