Type: Posts; User: erikl

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  1. Closed: Re: Optimized MinCap, Minres values for 10 MHz amp simulation using Spectre

    Due to very probable serial connection of RC elements I'd calculate with the 10-fold frequency, hence 100MHz. So I'd try e.g. with mincap=100fF and minres=16Ω (f = 1/2πRC).
  2. [SOLVED]Closed: Re: Common mode gain simulation for differential amplifier using balun

    In order to stay consistent with Ken Kundert's Test Bench description, you should name the input balun Bi (i for input) and the output balun Bo (o for output).

    Yes, I think so!
  3. [SOLVED]Closed: Re: Common mode gain simulation for differential amplifier using balun

    I think the second paragraph of 3.1 Gain in the a.m. PDF should read (only for the Balun nomenclature of your a.m. picture!):

    To measure the common-mode gain, set the AC magnitude on Vic to 1 V...
  4. Replies

    Closed: Re: ConnectLib files in ams simulation Cadence

    Yes. You have to create your own level converter - if the AMS lib doesn't offer one.
  5. Closed: Re: What is Double Snapback Characteristics in High-Voltage nMOSFETs

    Snapback - in this context - means the sudden receding of the voltage at a certain current, which generates a kink (or a knee) in the I-V characteristic of the device.
  6. Closed: Re: What is the difference between LVS and ERC ?

    - LVS means Layout versus Schematic comparison
    - ERC means Electrical Rules' Check
    - DRC means layout Design Rules' Check

    These all are necessary checks with their own rules' sets. Depending on...
  7. Closed: Re: How to change the m factor (multiplication factor) for Instances in cadence

    Depends on how you want the multiplication be done:

    Either m equal instances of the same device, then instantiate this device <1:m> times in parallel. Or you can multiply it by its Number of...
  8. Replies

    Closed: Re: Current reference design for CS-DAC

    1) I think your wp/wn ratio is too large. Increase your nmos widths, keeping the original w/l ratios.

    2) If you decrease the above widths ratio by this method, you should be able to keep your pmos...
  9. Replies

    Closed: Re: Generate pulses of different widths

    Use a piecewise linear (PWL) voltage-controlled voltage source (VCVS).
    Search for these abbreviations in your C@dence Virtuoso simulation engine docu.
  10. Replies

    Closed: Re: Factors deciding Silicon Wafer Thickness

    1. The wafer diameter (crash (concussion) safety during handling (manual or automatic) )

    2. The dice' separation method (scribe & break, sawing, etching)

    3. As thin as possible (silicon usage)
  11. Replies

    Closed: Re: Calibre Tool for DRC errors

    This depends on:

    - which physical design tool you are using
    - which DRC tool your PDK prefers
    - which (potential) foundry provides their Design Rules' Set for the PDK of your physical design tool
  12. Replies

    Closed: Re: Nand gate using bsim-cmg

    Either hspice didn't find the .include "modelcard.xmos" modelcards, or
    these modelcards do not contain the therein used nmos1 respectively pmos1 models.
  13. Closed: Re: Differences between Wideband & broadband RF Power Amplifiers

    I think so. At least both of them are sometimes used in the same connection. Some companies seem to make a difference regarding the application:

    Pasternack uses broadband amplifiers as...
  14. Replies

    Closed: Re: Nand2 gate in magic vlsi

    Seems you didn't apply a stimulus signal?
  15. Closed: Re: IC layout I/O design------power on control (POC) cell

    Depends. Maybe there's a pad cell available, which creates this signal (e.g. an LDO pad cell which creates the core Vdd from the pad Vddpst voltage. Its "power good" signal could be your POC). If...
  16. [SOLVED]Closed: Re: Connect rules are not found in your AMS installation? error

    Maybe you must state the path to these rules somewhere in the ADE setup?
  17. Closed: Re: DRC Error: N+SD Iso Psub tap spacing must be

    Not sure if I interpret your colors correctly. At the left side to me it seems you have an Nimplant within a Pimplant crossing the Nwell border (connected to the D? of the nmos, pls. see the picture...
  18. Closed: Re: DRC Error: N+SD Iso Psub tap spacing must be

    Did you connect the Psub via a contact to M1 to GND? If not, it doesn't work. If yes, you better provide an image of the field of your problem.
  19. Closed: Re: [Help] How to show all pins Proteus 8.0 in ISIS

    Seems already your trial was sufficient - at least to upgrade the title ;-)
  20. Replies

    Closed: Re: Slew rate for folded OPAMP with driver

    I think you must consider the output capacitance of the driving node (the output), too, in parallel. You could try it by adding a cap (to GND).
    BTW: Pls. adhere to the official...
  21. Replies

    Closed: Re: Extra layers in finfet technologies

    Foundries can name their layer names as needed. diffcon probably is a connection for a diffusion (which, itself, is an implant), so probably polycon is a connection layer to poly.
  22. Replies

    Closed: Re: No connection for Nwell

    Put an n+ implant region into the nwell and connect it via a contact to M1 and with it to VDD!
  23. Replies

    Closed: Re: Chemical for removing silk screen and solder mask layer?

    Try Tri or Tetra.
  24. Replies

    Closed: Re: Slew rate for folded OPAMP with driver

    Like always, the slew rate δV/δt = Iout/Cout .

    The current Iout of the output buffer is the adjusted current Ipre of the pre-amp stage (through M12, M10 ...) times the current gain by the W/L...
  25. Replies

    Closed: Re: CDM resistance calculation

    1. the outside HBM diodes must be able to stand several CDM voltage pulses
    2. the inner CDM diodes must be able to stand the limited current due to the CDM voltage spikes.
    If you know which...
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