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Type: Posts; User: mjuneja

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  1. [SOLVED]Closed: Techniques for logic cell estimation - FPGA

    Can somebody share what are the best techniques in FPGA design that can be used to estimate the logic cell utilisation in an FPGA even before the RTL is written in (VHDL or verilog) so that FPGA...
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    Closed: Re: Tracing internal signals in Modelsim

    "KEEP IIRC" property belongs to which process, I am using ISE design suite from Xilinx.
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    [SOLVED]Closed: Re: Rs232 is protocol or wiring standard?

    https://en.wikipedia.org/wiki/RS-232

    https://www.electronicshub.org/rs232-protocol-basics/
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    Closed: Re: Tracing internal signals in Modelsim

    In which file format do you save the waveform window set up, which can be recalled in the simulation run.

    And second thing, as already asked in post #4, how do you relate internal signal names in...
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    Closed: Re: Tracing internal signals in Modelsim

    Thanks to both of you..

    Both of these solutions proved helpful for behavioral simulation.

    But if I am doing post layout simulation the names of all the internal signals changes.

    So my query...
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    Closed: Tracing internal signals in Modelsim

    Hello

    I am running a simulation of a digital design for Virtex 5 FPGA in Modelsim simulator (PE student edition 10.4a).

    Currently I am able to trace all the top entity signals in wave window,...
  7. Closed: Re: Digital weighing scale maximum load capacity.

    See there are 2 things --

    1. How much maximum weight the weighing machine can sustain ??

    That depends on the capacity of the sensor being used which is ultimately decided by your...
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    Closed: Re: VHDL state machine execution

    Can you share the code of your state register and next state logic process.
  9. Closed: Re: Digital weighing scale maximum load capacity.

    Can you re-frame your question ..

    Are you talking about design parameters or something else..what are you planning to design.
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    [SOLVED]Closed: Re: Basic capacitor question

    900 V defines the maximum capacity of the capacitor. If you are charging using 500 V, it will get charged uptill 500 V.

    That is Q = 600uF x 500 V.
  11. Closed: Re: Cannot continue(fatal error) problems with lifo

    One thing I noticed in your code is that stack_ptr is not there in the process sensitivity list, I am not sure whether till 1000 ns your simulation results are ok or not.

    Second thing is since...
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    Closed: Re: setup violation in physical designing

    First of all it is important to understand which path in the design is failing, trace it back to RTL code and the verify what are the timing constraints that has been defined for that path in the...
  13. Closed: Re: Is logic cell a technology independent parameter

    I think logic resources utilized by the design depends on 2 things

    1. the FPGA used for design

    2. the IDE used to implement the design as different IDE tools uses different optimization...
  14. Closed: Re: Techniques to solve metastability issue in VHDL

    The double sampling you have shared works when you are dealing with signals crossing one clock domain and entering into other clock domain.

    And in that too clock to be used in the sampling FF...
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    Closed: Re: Output pixel larger than the desired pixel

    Can you please share the MATLAB code used for receiving the data as well as FPGA code used for sending the data ?
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    Closed: Re: 12 Hour Clock using VHDL

    I can't see any reference of "minute_out" in your code, please share the relevant section of code.
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    Closed: Re: Concurrent constructs in Verilog?

    Multiple always blocks as well as blocking assignments (describing combinational circuit outside always blocks) executes in parallel.
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    Closed: Re: 12 Hour Clock using VHDL

    I think tick_in should be included in the code.


    process(tick_in,reset,sec)
    begin
    if(reset = '1') then
    sec <= '0';
    elsif(rising_edge(tick_in))then
    if(sec = 59) then
    sec <= 0;
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    Closed: Re: What will be the logic ckt?

    Can you try a separate clock signal to provide edge triggering to run this logic ckt.
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    Closed: Re: What will be the logic ckt?

    I don't find any straight forward combinational circuit that can help you achieve this sort of output from signals A and B.

    But you can try some sequential circuit in which the output depends on...
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    Closed: Re: Clock tree synthesis

    Clock skew is the time difference in arrival of same clock signal at different components of a synchronous design, due to delays being added in clock path.
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    Closed: Re: RTL Coding HELP - Race Condition

    I don't find any problem in your explanation. It's completely fine to do that.

    Even you can simulate once and check, it will definitely work.
  23. [SOLVED]Closed: Re: Tracking states of FSM (finite state machine) in Modelsim

    Finally I got the answer to this question.

    So I found that there can be 2 scenarios while defining FSM:-

    1. If the total no. of states (except others) is 2, 4 , 8 , 16 or any 2^n ; then...
  24. [SOLVED]Closed: Re: Tracking states of FSM (finite state machine) in Modelsim

    Here is the code of FSM.


    --state_reg------------------------------------------------------------comm
    process(clk,rst_n,state_next) ...
  25. [SOLVED]Closed: Re: Tracking states of FSM (finite state machine) in Modelsim

    Finally I got the fsm encoding done.

    Actually in my case statement I had put a case of "when others =>", that's why it was not realizing that part of code as FSM.
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