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Type: Posts; User: MubarakKhan

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  1. Closed: In snapback mechanism how voltage reduces when parasitic NPN is turned ON?

    I'm reading the following paper about SNAPBACK

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    In the case of positive ESD stress, the...
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    Closed: What are biasing circuits?

    What are biasing circuits? All circuits involving transistors are called biasing circuits (or) circuits used to generate reference signals like BGR are biassing circuits?
  3. Closed: While checking LVS I got following error LOGS

    I'm using GPDK45

    Layout is LVS clean

    Error logs :
    __________________________________________________________________________
    ...
  4. Closed: Different isolation techniques used to isolate devices with different potential?

    what are the different isolation techniques used to isolate devices with different potential?
    like I Know about deep N-well, P-well is used to isolate the devices with different potential.
    are they...
  5. Closed: What is Double Snapback Characteristics in High-Voltage nMOSFETs

    I'm reading the attached document in that I didn't understand what is Snapback.
    when I search about Snapback it shows some basketball caps.
  6. Closed: What is the difference between LVS and ERC ?

    What is the difference between LVS and ERC?
    is ERC is part of LVS or it is a separate check?
    in Assura, I can see two-run options (Run LVS & Run ERC).
    with the help of switch option, I can check...
  7. Closed: How to create my own .lie file in cadence ?

    How to create my own .lie file in cadence ?
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