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Type: Posts; User: Puppet123

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  1. Closed: Physical Verification with TSMC65nm CRN65LP PDK

    Hello,

    This posting is similar to an earlier posting:

    https://www.edaboard.com/showthread.php?280164-Physical-verification-with-TSMC-CRN65LP-v1-7a-PDK

    I do not have the hcells file.

    How...
  2. Replies
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    214

    Closed: DNL/INL Measurement in Cadence for DAC

    DNL

    https://milindsweb.amved.com/Calculating_DNL_in_Cadence.html

    INL

    https://milindsweb.amved.com/Calculating_INL_in_Cadence.html
  3. Closed: Re: INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Hello,

    Your answer is nonsense.

    In the future, please answer the question being asked.

    That's all.

    Thank you.
  4. Closed: Re: INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Thank you.

    So, I use ramp or sine wave drive to determine my output and then use your script to turn it into a histogram in Cadence/Virtuoso?

    Then I post-process that histogram plot ?

    I...
  5. Closed: Re: INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Hello,

    Thank you - can you re-post the hard copy of your setting of "ADE>Tools>Monte Carlo"? They have been removed from the original post.

    So, basically, the procedure is:

    1. Run a Monte...
  6. Closed: INL/DNL Measurement from Cadence Spectre/Virtuoso Output

    Hello,

    I want to measure the INL/DNL of an ADC designed in Cadence Spectre/Virtuoso.

    I understand the methodology: apply an ideal DAC at the output, apply a ramp signal, or a sine wave and get...
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    Closed: LDO Simulation Output Results

    I attempted to design a PMOS Pass Transistor LDO and obtained the following result.

    I set the reference voltage to about 650mv and did a DC simulation.

    The regulated voltage starts up and then...
  8. Closed: Capacitor Selection in Sigma Delta Modulators

    Hello,

    I am designing 3rd Order, Single Bit, CIFF Discrete Time Sigma Delta Modulator.

    How to select the capacitors sizes for this design ?

    See attachment.

    CT - total of ff - feedback...
  9. Closed: Opamp - Gain/Phase Margin Swept versus Variable

    Hello,

    I want to use Cadence Virtuoso/DFII to find the gain and phase margin of an opamp swept versus the load capacitance (or any other swept variable).

    So, Gain and Phase Margin on the Y...
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    Closed: EKV to BSIM Model Conversion

    Hello,

    Is it useful or possible to convert CMOS EKV Model to BSIM Model ?

    I want to use the gm/ID sizing methodology and it is better with EKV.

    What is the reason that the EKV model did not...
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    Closed: Re: sfdr simulation in Matlab

    Just use Pretty FFT - found here:

    https://secure.engr.oregonstate.edu/wiki/ams/index.php/Matlab/PrettyFFT
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    [SOLVED]Closed: Re: Need RF examples lib.

    It is under : <InstallDIR>/tools/dfII/samples/artist/rfLib where InstallDIR is where your Cadence installation is.

    You can look for it.
  13. Closed: LDO Simulation - Cadence - ILoad vs. Vout - Line Regulation

    Hello,

    I would like to plot Iload vs. Vout for the Line Regulation for an LDO in Cadence Virtuoso and am wondering what the best approach would be.

    I can put just an ideal current source, Idc...
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    Closed: DNL/INL Using Cadence ahdlLib blocks

    Hello,

    I want to use the DNL/INL AHDL blocks in ahdllib in Cadence to measure the DNL/INL of an ADC.

    I use the ideal DAC to convert to digital then add the DNL or INL ahdlLIb block and a file...
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    Closed: Analog Layout - Multipliers and Fingers

    Hello,

    For Analog Mixed Signal Layout in CMOS in 65nm and blow, what finger size and multiplier should be used ?

    I have been told to avoid multipliers unless in cases of Common Centroid layout....
  16. Replies
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    Closed: Opamp Layout Example

    Does anyone have contents of this website saved ?

    http://www.doe.carleton.ca/~jlam/5808/A4/
  17. Closed: Semiconductor Industry future timeline for cmos 5nm

    Hello,

    We are already at 5nm in CMOS.

    How much longer with the modern day semiconductor industry last for ?

    5 years ? 10 years ? 2 years ?

    I am talking about Analog IC, Mixed Signal IC...
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    [SOLVED]Closed: Re: Phase Jitter Manual Calculation

    Hello,

    Try these two documents:

    Analog Devices - Jitter from Phase Noise (What you want)
    https://www.analog.com/media/en/training-seminars/tutorials/mt-008.pdf

    Silicon Labs - Jitter from...
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    Closed: Mentor Calibre in CentOS

    I am using a certain PDK in CentOS Linux to run Cadence 1.6.7 and Mentor Calibre 2015.

    It will not compile the PEX cal file, but a friend can get it running on Calibre 2014.

    Are their typically...
  20. Closed: Errors in Cadence Virtuoso/Keysight Momentum Dynamic Link/Momentum Setup

    Hello,

    I am getting the following errors when I run Momentum Virtuoso from Cadence Virtuoso Layout to do EM Simulation of Cadence Virtuoso Layout using Momentum.

    Does anyone know what they mean...
  21. Closed: Re: What is the best way to learn about PLL and DLL and their differences?

    Hello,

    DLL is mostly covered in books and book chapters along with PLL.

    Razavi has a good reference paper and tutorial on DLL in his book:

    Phase-Locking in High-Performance Systems: From...
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    Closed: Re: Cadence SPB Allegro and OrCAD

    I know that.

    The software is released together and your licensing determines which of Allegro PCB Editor or OrCAD PCB Editor you can use.

    This is what I was asking.
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    Closed: Cadence SPB Allegro and OrCAD

    Hello,

    Is the Cadence SPB Allegro and OrCAD release one that includes BOTH OrCAD and Allegro ? Or is it called OrCAD and they just put the Allegro name ?

    I would like to purchase Allegro but I...
  24. Closed: Perl/Python Scripting for Analog/Mixed Signal Design

    Hello.

    I am interested in learning Perl/Python Scripting for Analog/Mixed Signal Design.

    Are there any good resources about this anywhere ?

    Books, Online courses, or other resources online....
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    Closed: Re: VCVS in LTSPICE as a 1 bit Comparator

    Hello,

    Thank you for your replies.

    It is for an MDAC for a Pipeline ADC simulation. I need a 1 bit comparator for the 1.5 bit Pipeline ADC stage.
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