Search:

Type: Posts; User: anusha vasanta

Page 1 of 2 1 2

Search: Search took 0.00 seconds.

  1. Closed: how to read data available in nibble format

    hi all,
    i had nonce of 104 bits and header of 240 bits here i have to read these inputs but i had these values available in the format of nibbles when i was giving them it was showing error.
    how...
  2. Closed: how to identify the no.of clock cycles during simulation of design?

    Hi all,
    i had a very basic doubt as per the design i can understand the no.of clk cycles, but during my simulation how can i identify simply the no.of clock cycles my design is taking. any easy...
  3. Replies
    1
    Views
    747

    Closed: writing the test bench in verilog

    Hi all,
    can anyone suggest me the best way of writing test bench for verifying all of the corner cases.
    you can put any link or some small gist regarding it. thanx in advance
  4. Replies
    3
    Views
    672

    Closed: Re: asserting valid signals

    thankyou. but here both are asserted and deasserted during posedge of clk how the actual process is gng on internally.
  5. Replies
    3
    Views
    672

    Closed: asserting valid signals

    Hi all,
    is this a proper way of asserting and deasserting my valid signal.



    for (i=0;i< No_Patterns;i=i+1) begin //apply inputs
    @ (posedge clk)
    #Clk2Q
    data_valid_in = 1; ...
  6. [SOLVED]Closed: Re: generate for loop inside a generate if loop

    thanks all,
    i am a new learner not a s/w hammer.thanks for all all of your suggestions.
  7. [SOLVED]Closed: Re: generate for loop inside a generate if loop

    thanku all for ur valuable guidance.
    1.what my doubt is can we write a for loop inside a generate if condition?

    2.if i had a code of multiple assign statements with in a generate block the result...
  8. [SOLVED]Closed: generate for loop inside a generate if loop

    Hi all,
    can we use generate for loop inside a generate if loop which is outside of my always block, basically i want some instantiation using my for loop and here i had a register which i need to...
  9. Closed: Re: how to ctrl the operation of register

    can u suggest any good books which even had verilog-2001 constructs
  10. Closed: Re: what is the main essence of generate block and how is it useful??

    thanku then in how many clock cycles we can get the o/p for a generate block of above kind.
  11. Closed: how to ctrl the operation of register

    HI everyone,
    i had a doubt help me, i had a tmp_reg of 128 bits in starting time that tmp_reg should contain a mic value of 128 bits , and from next onwards it should contain some other result,...
  12. Closed: what is the main essence of generate block and how is it useful??

    genvar a;
    generate
    for(a=0;a<=7;a=a+1) //converting input data_in bits into bytes format
    begin : MEM
    assign data[a]= data_in [((a*8)+7):(a*8)]; ...
  13. Closed: Re: instantiation with in an always block

    Haa i know that we can't use instantiation inside an always block but heard that gen block can be written inside always block so i got the doubt of that kind.
    Actually i had a tmp_reg contains one...
  14. Closed: instantiation with in an always block

    Hi all,
    is there any way to do the instantiation inside always block, here i had a code which had a tmp_reg first it should have one value and next it should take some other how could it be...
  15. Closed: issues on data passage through wires

    hi all,
    i had a register of 30 bytes which is created by me from this reg i need to pass the data of 30 bytes to another module. for this i had taken 240 bits of wire, is it okay or entire 30...
  16. Replies
    6
    Views
    1,102

    Closed: Re: Tools supporting verilog-2001

    thanku all for your support,
    the doubt is cleared. but there was a problem when i wanted to simulate my s.v code.previously i had done all the flow using synopsys tool but as it is for fpga purpose...
  17. Replies
    6
    Views
    1,102

    Closed: Tools supporting verilog-2001

    Hi all,
    i am using xilinx tools for my rtl implementation. what versions of isim do support verilog 2001 also.because i was using xilinx 13.3 in that it was saying that part select of memory is...
  18. Replies
    2
    Views
    777

    Closed: pipelining concept in rtl

    Hi all,
    do pipelining reduces the no.of clock cycles in rtl??
    what do actually pipeline means in verilog is it implementing non-blocking statements or anything else??
    thanx in advance
  19. Replies
    2
    Views
    1,212

    Closed: regarding time-scale in verilog

    Hi all,
    can u explain me how the 'timescale 1ps/1ps will be evaluated.
    thanx in advance
  20. Closed: Re: Best Editor for Verilog Code Navigation

    vi editor i think
  21. [SOLVED]Closed: Re: Automating RTL simulation using VCS of Synopsys

    using dc-compiler for synthesis you can happily write a make file. for your first question whenever your simulation got completed it will generate a batch mode result.with those results you can...
  22. Replies
    12
    Views
    1,702

    [SOLVED]Closed: Re: Assign statements dependency on clock

    thank you. i understood that my doubt is we can reduce our clk cycles right using assign statement ??
    here i had some 24 bytes of data i had to pad some 3 bytes of zeros to this 24 bytes of data...
  23. Replies
    12
    Views
    1,702

    [SOLVED]Closed: Re: Assign statements dependency on clock

    then the assign statements will never depend on clk right. then using this our code will get optimised or else more assign statements will make our netlist not efficient.
    Here what i want to say...
  24. Replies
    12
    Views
    1,702

    [SOLVED]Closed: Assign statements dependency on clock

    Hi all,
    does assign statements depends on clk during our module execution. As we will never include our assign statements inside an always block.if they don't depend on clock is they are...
  25. Closed: main coding difference b/w Big-endian and Little-endian

    Hi all,
    here i was taking my reg as
    reg [7:0] data [63:0] this is a big endian then what is the difference b/w reg [0:7] data [63:0] is this also a big endian or the representation is not...
Results 1 to 25 of 34
Page 1 of 2 1 2