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  1. Closed: A step-by-step Guide to SystemVerilog Interfaces - free Webi

    http:// www.cvcblr.com/events__news
    Date : January 28, 2010
    Time : 9.30 AM – 10:30 AM India Standard Time

    Date : January 28, 2010
    Time : 3:00 pm - 4:00 pm Central European Time

    Date :...
  2. Closed: Re: ESL and Verification

    Hi thank you for your reply
    my question is
    if
    1.ESL to RTL(using some tool) is possible
    2.formal verification between esl and rtl is also possible..
    then functional verification will happen at...
  3. Replies
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    Closed: Re: Code coverage ius82

    I use next ncelab coverage options:
    -coverage all -covdut dut_name[/quote]

    Try:


    nchelp ncelab COVSCNDRY

    My guess is you use svpp flow, but it is a wild guess. Look at irun flow or best...
  4. Closed: Re: Cadence Systemverilog Testbenches: bind program blocks

    If you have the energy to investigate, I highly recommend you look at OVM - its test (OVM_TESTNAME) mechanism is precisely meant for this. I don't know how well it works on IUS< but works fine on...
  5. Closed: Re: Help from knowledged ppl on choosing VLSI specialization

    Hi Josh,
    If you are looking for a serious job oriented course consider looking at our EIC - it is not traditional training, rather "incubation" as we put you on to projects and provide various...
  6. Closed: Re: Co simulation of SystemC files with VHDL testbench

    Dor,
    Look at their manual, I found: VHDL Instantiating SystemC

    We have Verilog/SV-SystemC training examples @ CVC, can quickly make it to VHDL if needed. Contact me offline info@cvcblr.com if...
  7. Closed: Re: for ti interview

    Is it for VLSI? If so brush up Verilog/VHDL. If you have any higher level verification experience like E/SystemVerilog/PSL that will be a GREAT advantage. You may also consider our internship program...
  8. Replies
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    4,478

    Closed: iivdt

    Pradeep,
    We value your response, thanks!

    See my replies embedded:



    Yes that's typically meant for working professionals (what we call as Corporate customers).
  9. Closed: fpga projects

    If you are genuinely interested in DOING it yourself and are looking for ideas & guidance contact us via www.cvcblr.com. If you are looking for pre-cooked ones with report etc. ready - don't even...
  10. Replies
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    Closed: Re: Learning SystemC

    We (www.cvcblr.com) have a course on SystemC starting end of Sep 2009 if anyone is interested!


    Regards
    Ajeetha, CVC
    www.cvcblr.com
  11. Replies
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    1,618

    Closed: ovm forum

    Hi Suyog,
    I believe you have spoken to my colleagues about this. CVC (www.cvcblr.com) has been pioneering this domain and have the right setup you are looking for. We have been doing successful...
  12. Replies
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    1,670

    Closed: Re: Required : Book on Assertion

    Kindly send an email to: training <> cvcblr.com or cvc.training@gmail.com.

    Contact Jagadeesh @ 080-42134156, 9620209223 or Bagath via: 9916176014 for exact pricing details. For others, you may...
  13. Closed: gate level synthesis

    Try turning on -debug or -debug_all for the SAKE of shutting down optimization and see if that helps. If yes, then we can further nail it down to specific code.

    Best is if it reproduced in a small...
  14. Replies
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    4,478

    Closed: system verilog training in india

    Sorry to intervene on a customer-vendor related thread, but wanted to clarify few things. First of all YES, we at CVC offer some of the BEST courses needed by experienced folks in the industry (and...
  15. Replies
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    Closed: verilog code

    Try verilog-mode.com - not as great as VHDL mode, but does a decent job.

    Ajeetha
    www.cvcblr.com
  16. Closed: embedded system projects

    You may want to explore emerging Assertions + AMS Verification related projects such as:

    http://www.vhdl.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/fslASVApropertyRenderings_1.0.pdf
    ...
  17. Closed: vish-4014 no objects found matching

    Try using:



    vlog -voptorgs=+acc

    Issue maybe to do with the vopt flow.

    Ajeetha, CVC
    www.cvcblr.com
  18. Replies
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    Closed: Re: DEBUG THIS CODE...IF POSSIBLE

    If you can post your sample trace/testbench code as well, maybe someone can point you what's wrong.

    Ajeetha, CVC
    www.cvcblr.com
  19. Replies
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    3,371

    Closed: ph d in electrinics + india + partime

    Depends on which city you work in. In every major IT city there is IIT/IISc and there are some good professors. The individual websites shall give more details too. Personally I know Prof. Kamakoti...
  20. Closed: get system verilog constant in vhdl

    Depends on the tool you use. If you use Questa, yes, use:



    vcom -mixedsvvh

    and then the data types, constants declared in VHDL are visible in SV. There are some restrictions as well, read...
  21. Replies
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    Closed: Re: $random & $urandon - systemVerilong

    SystemVerilog LRM has a detailed section on random stability to which this question kind of belongs to. It dictates that implementations shall be random stable (under few conditions, see LRM for...
  22. Replies
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    Closed: modelsim encrypted verilog

    Sunil,
    It maybe due to the vopt flow. Can you try using "vsim -novopt <top_level>"?

    Ajeetha, CVC
    www.cvcblr.com
  23. Replies
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    2,757

    Closed: eof: syntax error modelsim

    It is a syntax error in your Verilog/SV source code. Show us your code if you need more help.

    Ajeetha, CVC
    www.cvcblr.com
  24. Closed: Re: ncxlmode help

    Did you try removing the INCA_Libs and run it again?

    Ajeetha, CVC
    www.cvcblr.com
  25. Replies
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    Closed: Re: Problem in Simulation using ncsim

    Do:



    nchelp ncelab DLMKDF


    (Or some slight variant of that, check doc). Looks like your NC installation is incomplete, perhaps some ENV setting going wrong?

    Ajeetha, CVC
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