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  1. Replies
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    Closed: Re: Assigning a null array in VHDL

    A NULL array is defined as array with 0 length. ie. one with a range where 'left is higher than 'right in the case of to, and 'left is less that 'right when using downto.
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    Closed: Re: Assigning a null array in VHDL

    I dont understand what you mean, I showed you how to define the constant.
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    Closed: Re: Assigning a null array in VHDL

    You'll need to create a null constant (or signal):


    constant NULL_ARRAY : array_1d_unsigned(1 to 0)(1 to 0) := (others => "");

    ..

    x => NULL_ARRAY,
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    Closed: Re: vhdl problem debug help please

    Put the counter in a clocked process - you cannot do a counter in a combinatorial process. It is not updating because you forgot to add count to the sensitivity list, but if you do, you'll get an...
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    Closed: Re: Logic duplication and optimization

    Actually, I need to add something to this, as I have been bitten by the following before, and I was just writing some similar code. This is a code issue rather than synthesis/optimisation issue.
    ...
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    Closed: Re: Logic duplication and optimization

    Synth tools would probably do a better job of this than you, and you may end up preventing some optimisations.

    As dave says, just make it clear and readable. Id argue the first instance is most...
  7. Closed: Re: How I can make use of the resources of only certain regions of the device in Viva

    What is your goal?
    It is normal that a implemented design changes between builds because placement relies on a random seed. If the source code, constraints or seed change, then the final result will...
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    Closed: Re: AXI4 VHDL BFM Options

    That UVVM article is very gushing an implies that OSVVM doesnt have any reporting. OSVVM has had reporting and alerts for a long time.

    You can get the OSVVM documnentation here:...
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    Closed: Re: AXI4 VHDL BFM Options

    The Xilinx SV VIP is pure SV, dont bother trying to use it in a VHDL testbench. Either write a SV testbench or find another BFM.
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    Closed: Re: Reduce Net delay in FPGA synthesis?

    Without a constraint the tool will put little effort into the routing. It will just place two luts somnewhere and a route between and then thinks its finished.
    With a constraint, it will place the...
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    Closed: Re: AXI4 VHDL BFM Options

    2019.1 now has some quite good VHDL 2008 support in synthesis (generic packages, generic types and functions as generics). But the simulator is way behind, which seems very odd.
    Xilinx even provide...
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    Closed: Re: AXI4 VHDL BFM Options

    Xilinx is all sv now and not providing vhdl models for anything. You're stuffed if you only have avhdl license
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    Closed: Re: AXI4 VHDL BFM Options

    I honestly rolled my own (in VHDL) using OSVVM (for scoreboarding and reporting) because all you can get free online is AXI4s and lite, while I needed full AXI4. AXI4L is just a restricted version of...
  14. Closed: Re: FPGA program has some hard to trace glitches

    Looking at a waveform without seeing or understanding what you're actually trying to do doesnt tell us a lot. So far, to summarise, you have asked - "My design doesnt work, whats the problem?" and so...
  15. Closed: Re: Good verilog or vHDL book for implementation of mathematical operations

    Most books around are several years old. Technology moves on. You can get good performance from good RTL code without having to hand place or any optimised LUT or DSP design. Inference is pretty good.
  16. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    I agree with ads-ee. You should be able to read all the data into an array in zero time. I would usually do this in an initiallisation function rather than a process. If you are relying on the 1ns...
  17. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    I dont quite know what you mean? A ROM in an FPGA is just a BRAM/M9k whatever thats pre-loaded with data with the write-port not connected. This can be infered from HDL as a constant with synchronous...
  18. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    The problem is you're trying to create an array before you know the size. So if you need to read the whole file into an array you can do one of the following:
    1. Read the file to see how big it is,...
  19. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    You should not create a type from a signal. Your array is only length 1 (0 downto 0). You should use some constant value to set the length of the type
  20. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    you can call a function during initiialisation:


    function some_init_func return integer is
    begin
    return 10;
    end function;

    constant SOME_CONSTANT : integer := some_init_func;
    signal...
  21. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    What do you mean by "doesnt seem to open"? Does it throw an error about the file not existing? Is there no stimulus? Please explain the problem or show the error.
  22. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    array is a reserved word for the creation of a type. So it cannot be used as an object name.
  23. Closed: Re: What is the future of Boolean algebra-based languages and methodologies?

    Possibly, but nothing that is public afaik.
    Remember any radical change is not going to be bought, and there wont be any experience with it. Its a chicken and egg problem.
  24. Closed: Re: What is the future of Boolean algebra-based languages and methodologies?

    Intel are struggling with their 14 and 10nm chip fab. They have stuff to market now they were trailing 4 years ago and its about 2-3 years later than planned. They are going after the server market....
  25. Closed: Re: Problem calling a function from my vhdl project in Vivado.

    The best rule for converting to VHDL is to understand the code and re-write in VHDL. Direct port is always going to be a mess

    That error is because you're using VHDL 2008 syntax. The Vivado...
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