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Type: Posts; User: tkbits

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  1. Replies
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    Closed: Re: two's complement multiplication

    To multiply two's complement, the sign bit must be treated differently.

    For any multiplication of two n-bit numbers, the least significant n-bits for two's complement and unsigned numbers are the...
  2. Closed: Need help to simulate the verilog code given below

    always without sensitivity list is a forever loop?
  3. Closed: Re: problem with always block and sensitivity list

    Yes, that will work.
  4. Closed: Re: problem with always block and sensitivity list

    To update on the same clock edge, don't use the clock for the second signal.

    It seems that all the signals in the tests are clocked. If so, the Forward outputs will always change one edge after...
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    Closed: Re: Really simple question: Register behavior

    By itself, the register does not produce a 1-cycle delay.

    The 1-cycle delay is the delay between the generation (not the inspection) of D from the previous edge and the new edge - yielding a...
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    Closed: Re: Idiot's Guide to FPGAs Please!

    You do not build loops in FPGAs.

    Loops are replaced by control signals, and registers which are allowed (as dictated by control signals) to update themselves only when a clock signal changes...
  7. Closed: what is the protected type of shared variable?

    They don't synthesize because it requires adding arbitration logic.

    Asynchronous arbitration can be done by a request-acknowledge protocol.

    Synchronous arbitration can be performed by choosing...
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    Closed: Re: regarding start of frame packet in USB

    Devices do not generate SOF. Only Hosts (root controllers and hubs) generate SOF. If you build a full speed (12 Mbps) device, the Host will send SOF to your device.

    If you are building a Host (for...
  9. Closed: Re: asynchronous bus multiplexer in verilog: always+wire

    The left hand side of an assignment within an always must be "specified" as reg. Whether it is registered or not depends on whether the sensitivity list has signals listed as posedge/negedge or not....
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    internal tri-state inside xilinx

    The Spartan 3 does not have any internal BUFTs. Synthesis will convert BUFTs to MUXes, but only if the option is enabled.

    If you have a 16-bit bus with 32 sources of data, you will need 16 of the...
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    Closed: Re: Confusion in pins of FPGA kit and Chip pins

    With the latest versions of ISE, you will need to amend the pin numbers by adding "p" (as in the data sheet), as follows:

    Net "CLK_4M" loc = "p77";
    Net "out" loc = "p204";
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    Closed: pins for fpga

    If you're using ISE, each line starting with "Net" is placed in a UCF text file. Include only the lines that are needed.

    For example, you probably want to use the onboard 4 MHz oscillator for your...
  13. Closed: Re: Cyclic Reduancy Check

    The CRC division is not numeric. It is polynomial division with Boolean coefficients. The LFSR technique is a direct translation of the polynomial division, using XOR to do the "subtraction".
  14. Closed: Re: Why the data can’t be written into EEPROM?

    Time.

    The write time is much slower than read time. Completing the I˛C transfer only starts the write cycle.

    Some chips will not acknowledge while they are in the write cycle, you can...
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    Closed: i2c start detection

    Your posted code is clocking on SDA_IN instead of SCL.
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    Closed: ps2 keyboard vhdl

    playerAkeys(4) is only one bit of data, not 4. Note that PS/2 scan code is 8-bit. You need a multi-bit register, and optionally, slice notation: playerAkeys(7 downto 0).
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    Closed: How to design a digital adder??

    You are not being asked to design an adder.
    You are being asked to design a circuit from a truth table.
    The circuit, by instructor's choice, is an adder.
  18. Closed: variables in vhdl

    It only captures the input when you transition into state st02.

    Move it within the rising-edge IF, but before or after the CASE.

    You can also put it in another process separate from everything...
  19. Closed: Re: Verilog Question - sequential order vs parallel

    By "pressing a button", I assume you are using real hardware.

    Are you using the button to drive the clock signal?
    If so, you need to debounce the clock signal.

    If not, are you driving the...
  20. Closed: Re: State Machines

    You have feedback with

    count <= count + 5;

    This is because an adder is not a sequential circuit - the adder is combinational, built with AND, OR, and NOT logic, and no registers.

    This is...
  21. Closed: Re: State Machines

    A process is effectively an eternal loop. When there is no feedback, the process appears to act like an "execute once" process. However, when you have feedback (a signal appears on both sides of the...
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    Closed: Re: Strange calculation of numbers in VHDL code

    There are only two of the "(" characters between * and C_NB.
    The corrected grouping

    2 * ((4 + 1)/2) * 2 - 1

    evaluates to 7.
  23. Closed: logic not match

    <intset_0> is intset(0).
    <intset_3> is intset(3).

    Those are warnings, not errors.
    When you get this warning, it is because every usage of the "duty" entity uses "preset" values with those bits...
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    Closed: twos complement format

    Here is how the MSB inversion works...

    I'll use 3-bit numbers to keep it short.

    Notice that the INV column is created from the BIN column by inverting the MSB only.

    The 2-COMP column is the...
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    Closed: abs twos complement

    Can you give examples of what your results ought to be?
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