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Type: Posts; User: bking

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    Closed: Re: Difference of LVDS, LVPECL, HCSL, LVCMOS

    This has an overview of levels: https://www.ti.com/lit/an/slla120/slla120.pdf

    This data sheet has a table of thresholds and levels:...
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    Closed: Re: Identify capacitor with marking code L62 104

    The 104 is a 100nF / 0.1uF. The caps are typically marked with the first two digits significant and the third digit indicates # of 0's to follow.

    The L62 may be a lot # / date code for a...
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    [SOLVED]Closed: Re: FPGA Kit Recommendation

    From your attached report, you had already selected a device otherwise it could not have know the percentages. What was that one? Once you find that you can then see what is offered in that family....
  4. Closed: Re: [moved] Lattice CPLD Reconstruction and porting

    Xilinx's ISE webpack or some other stand-alone tool has a tool for converting ABEL to VHDL (and probably Verilog). It just happens that I used it for a Lattice CPLD as well. It flagged hardware...
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    Closed: Re: Motion Detector Alarm Timer Modification

    Normally the motion senor is connected to an alarm panel that will respond to the temporary activation of the relay and latch the alarm. It seems like the OP is looking to avoid the panel entirely...
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    Closed: Re: XC9536XL programing by DLC9G

    Since you have checked the voltages I'll ask the most obvious question - are you calling out the right part / using the correct bsdl file? The part where it asks if version 0101 is supported could be...
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    Closed: Re: Spartan-6 Servo Control

    Have you tried checking the signals to the servo with a scope to see if they are there? Are you using the correct pins on the header?

    Also, search for info on using clock enables with one clock...
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    Closed: Re: Variable gain through a microcontroller

    The AD5290 will accept +/-15V supplies.
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    Closed: Re: Information about a device

    If you didn't know what it was, why did you buy it?
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    Closed: Re: Modbus Communication circuit

    Are you providing the Common connection on the isolated bus side? That would be the GND2 in your schematic. On the non-isolated version you are likely picking it through other means. When you try the...
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    Closed: Re: Dual flop synchronizers and mtbf

    This paper has diagrams that may help: http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf
  12. Closed: Re: Schmitt Trigger vs. Rails vs. Mark/Space Ratio

    I'm going to make some assumptions... since you refer to Mark & Space, this is serial communications. From the nominal +/- 12 I'd guess it's 232? The thresholds for 232 are +/- 3V, so you could have...
  13. Closed: Re: Doorbell needs to be stepped up to 24v for Ring, but what about solenoid in chime

    Did you misread that and it's actually 30 VA? About 1-1/2 amps seems more in line with doorbell transformers.
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    Closed: Re: MachXO2 and SFP transceiver data issues

    This was the first thing that came to mind. You'll likely need to recover the clock from the RX data.
  15. Closed: Re: Connection for unused dual purpose pins of CPLD

    The "data sheet" is really more of an overview. Try this one: User Guide
    Look at the section for "Terminations" and I think all of your questions will be answered, plus allow you some options that...
  16. Closed: Re: shift register , i have troubles when creating components please help!

    It doesn't look like all of your ports being assigned.


    From Final Design:


    u2:shifter_unit port map (clk1,il,ir,S(3 downto 2),A(3 downto 0),q(3 downto 0));


    From Shift Reg Code:
  17. Closed: Re: Want to convert 32 bit data into 4 group of 8 bit data for UART

    Do you really mean to send bits 15-8 (i=1) before sending bits 23-16 (i=2)? Should they be swapped?
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    Closed: Re: I2C delay between SCL and SDA

    If you only delay the data then you will likely have no clock to shift it out with, assuming you are using SCL. SCL is not a constant clock.

    Can you explain why you need to delay the data? Maybe...
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    Closed: Re: I2C delay between SCL and SDA

    The process isn't being clocked by your 50MHZ clock. You are "clocking" it with changes on SCL_OE and SCL.

    Also, the check of DELAY should be 49, not 50. Remember that you are starting at 0 and...
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    Closed: Re: Spartan - 3A ADC and DAC interface not working

    Line 181: AD_CONV <= '0' after 5 ns;
    Don't think it's your problem, but that's not going to synthesize a delay.

    You might also look at your use of variables. A quick scan through and I can't see...
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    Closed: Re: What is the definition of RS232 DB9 female?

    While a terminal is, by definition, a DTE, what you have is not a DTE or DCE as the DCD and RI signals are in the opposite direction of CTS and DSR on your schematic when they should be the same...
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    Closed: Re: What is the definition of RS232 DB9 female?

    You still have most of the connections on the 9 pin reversed in direction. See post #10. You will never get flow control because nothing ever drives CTS, and RTS is being driven from both ends. This...
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    Closed: Re: What is the definition of RS232 DB9 female?

    Most of the directions on your 9 pin are in the opposite direction that they should be for a female connector if you were trying to follow the standard. If you are trying to connect to a DE9 male...
  24. Closed: Re: Can't get Spartan 3E to talk over UART to PIC246FJ128 UART

    Not much info to work with, so I'll ask something basic... is the parity set the same (or is parity even used) so the RX is looking for the same number of bits as the TX? Do you have an extra...
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    Closed: Re: Comparator with output to logical ground?

    LM339?

    Quad, open collector output
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