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  1. Closed: Re: The difference between '|' operator and keyword 'or'

    see this: http://www.asic-world.com/verilog/operators.html

    click on logical operators and on bitwise operators. the difference should be clear.
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    Closed: Re: Boundary Cell in Core Chip

    both assertions are incorrect. endcap cells are about well termination and timing consistency, regardless of cell location (near or far from an edge). welltaps are about bulk/well connections, not...
  3. Closed: Re: Preferred shell for scripting, csh or bash?

    there is a lot of legacy stuff in environment scripts and tool installation scripts. so we keep using the same stuff over and over.
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    Closed: Re: Timing Closure on metal filled GDS

    try the command defIn
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    Closed: Re: Timing Closure on metal filled GDS

    In cadence environment (innovus), you are supposed to import a DEF file with the externally-generated fill shapes into the design. timing analysis takes care of the rest.
  6. Closed: Re: Why set_max_fanout constraint in design compiler ?

    max_fanout is a type of DRV, just like max_tran and max_load. It made sense some 20 years ago when you could count the number of gates a std cell could drive. Modern std cell libraries don't care...
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    Closed: Re: ISCAS 89-s38417 testbench required

    bench files are old school netlists, they have no input vectors in them. i.e., they are not testbenches.

    - - - Updated - - -



    to the best of my knowledge, such testbenches do not exist. at...
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    Closed: Re: Clock Tree Synthesis

    before CTS, it is assumed the clock is ideal and reaches every single flip flop at the exact same time. In reality, after the CTS, there are small differences between clock arrival time at the nodes...
  9. Closed: Re: How D flip flop can hold output until next clock cycle when it is level firered.

    you need to understand the difference between latch and flop, level and edge.
  10. [SOLVED]Closed: Re: Design not simulating for different technology node

    I need to know a lot more about the setup. My first comment is that if you just take the testbench as is, it is unlikely to work for both netlists. I assume the 28nm version is much faster, and that...
  11. Closed: Re: What is the name of this transistor package?

    I call it "little annoying thing I cannot solder to my board" package. Hope it helps. :)
  12. Closed: Re: why is write delay low for 6T SRAM cell compared to 8T SRAM cell ?

    not to mention that delay is only part of the equation. SRAM compilers usually offer low and high density designs (rings a bell?) as well as single and dual port. delay becomes rather irrelevant...
  13. Closed: Re: [ Describing PG Pins at RTL Level UPF ]

    This is so confusing. What tool are you using, to begin with? What step of the flow are you doing? I can't think of any tool that takes RTL and UPF files.
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    Closed: Re: Innovus CTS .tcl Script Qustions

    I believe the tool is now able to find all clock roots automatically. Maybe they are inferred from the SDC commands.
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    Closed: Re: Innovus Command Questions

    Cadence has a really terrible time keeping the documentation synced with the new versions. Just stop using these commands and look for the new equivalent ones.
  16. [SOLVED]Closed: Re: Short violations in Innovus (due to special route)

    Check the well connections for these cells. Make sure the pins are named the same way as in the std cells. Just a hunch.
  17. [SOLVED]Closed: Re: Short violations in Innovus (due to special route)

    - check global net connections twice, and then check again. I don't understand your description of this internal power net and why that would be a problem.
    - run real DRC, don't trust Innovus DRC.
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    Closed: Re: Realistic Monte Carlo setup

    I could see Case 2 generating a wider distribution than Case 1, i.e., more pessimistic. My understanding is that this is exactly what foundries are trying to avoid when they recommend Case 1. I would...
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    Closed: Re: Realistic Monte Carlo setup

    Well, yes and no. Foundries recommend a mix of global and local MC, just like the OP mentioned. In my experience, case 1 is the prefered method these days. Based on the terminology I am almost...
  20. Closed: Re: Does Opentimer tool for STA support VHDL netlist

    even if it doesn't, converting a netlist from vhdl to verilog is rather trivial. Both DC and genus can do it for you.
  21. Closed: Re: DIE Size calculations in TSMC22ULL GF""FDX

    Not sure we can share previse numbers without giving away specifics of the technology. You can typically find some *rough* numbers in the marketing material/press release when the nodes mature into...
  22. Closed: Re: CPU, DRAM, VNAND - why can't they be integrated together on a single SoC?

    dick's answer is really thorough. it's all about the trade-off of market needs vs cost. we are not in a situation where most customers would benefit from embedded DRAM or NVM, so you got to pay a lot...
  23. [SOLVED]Closed: Re: CDC RTL Simulation vs non-CDC RTL Simulation

    it's not about the simulator support, it's about how the gate is described in verilog. check the .v file that came with your std cell library, it might account for metastability in very funky ways or...
  24. Closed: Re: Are parallel universes source of high fault coverage of sequential ATPG

    no. .
  25. [SOLVED]Closed: Re: Derate Factor while calculating delay

    derate factor is helpful for some simple rule of thumb estimation here and there. say, you are porting your design to a new library that is promised to be 10% faster. you can use the old library,...
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