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    Closed: Liberate - Custom Cell Characterization

    Tools and Tech:

    ST 65nm | LIBERATE Library Characterization Platform (x86_64) 12.1.4 (altos 121) | Cadence Virtuoso 6.1.5-64b | Calibre Interactive - PEX v2012.4_16.11

    I am trying to...
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    Closed: Synopsys Technology File (STF)

    I am using a memory IP block from STM. The manuals of the memory IP has talked a lot about Synopsys Technology File (STF), though, with no info on how and where to use it. Among all files related to...
  3. Closed: Re: Timing issues in netlist simualtion - SDF simulation of IP block

    Synthesizing the IP block, almost all paths to the IP are unconstrained. there is no mismatch between netlists and sdf file. All those errors when reading sdf file are starting from the line that the...
  4. Closed: Timing issues in netlist simualtion - SDF simulation of IP block

    TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm

    Hi

    I am running some timing simulations on my design and have some doubts and issues with the results.
    1- My...
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    Closed: Re: synthesized netlists simulation issue

    Thanks for your reply.
    I am wondering how this effect can be avoided, meaning in synthesis flow how I can control the paths somehow to avoid receiving some invalid midterms. To my specific design...
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    Closed: Re: synthesized netlists simulation issue

    Hi
    I tried to post the image inline with the message, probably something went wrong.
    I attached the image again to this reply.
    BR
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    Closed: synthesized netlists simulation issue

    Tools: Synopsys design_vision 2013 / Questasim 10.0d / tech ST65nm

    I have several issues with simulation of my synthesized netlists from design_vision.
    1- As a simple design, I synthesized a...
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