Search:

Type: Posts; User: ads-ee

Page 1 of 20 1 2 3 4

Search: Search took 0.06 seconds.

  1. Replies
    129
    Views
    6,023

    Closed: Re: AXI arvalid signal issue

    Posting that much code in a syntax window is ridiculous nobody is going to want to scroll through 1631 lines of code to look for one signal, that is not even in the posted code (I had to copy the...
  2. Replies
    11
    Views
    321

    Closed: Re: How do ESD monitors work ?

    It is interesting that the website the picture post is from is a website that has a description of the methods used to detect a person in the "loop"
    ...
  3. Replies
    12
    Views
    567

    [AVR]Closed: Re: Temprature sensors. LM35 vs MCP9700

    The other option to "calibrate" either of the parts is to use a reference like the digital sensor in the room as the "golden" reference and adjust the reading accordingly with an offset. This only...
  4. Replies
    12
    Views
    567

    [AVR]Closed: Re: Temprature sensors. LM35 vs MCP9700

    I don't see why there is anything wrong between the two, they are tracking very well.

    I just see a need for calibration being done on the sensor(s).
  5. Replies
    13
    Views
    850

    Closed: Re: Error :Syntax error near "module"

    they are equivalent, but I would suggest never writing stuff like this:

    if (not app_en = '1') and (not app_wdf_wren = '1') then
    state <= READ;
    end if;
    It doesn't follow a KISS rule.

    It...
  6. Replies
    13
    Views
    850

    Closed: Re: Error :Syntax error near "module"

    You shouldn't be assigning anything to a reg in it's declaration, this may or may not work in an FPGA some tools will use that as the power up state of the register.

    If you need to set a register...
  7. Replies
    13
    Views
    850

    Closed: Re: Error :Syntax error near "module"

    You should read a verilog book are at least an online tutorial


    reg [127:0] data_to_write = {32'h00AAAAAA, 32'hAAAAAAAA, 32'hAAAAAAAA, 31'hAAAAAAF, sw};

    to concatenate stuff in Verilog just...
  8. Replies
    13
    Views
    850

    Closed: Re: Error :Syntax error near "module"

    Excellent catch... here is what Modelsim shows when compiling in verilog and vhdl

    C:\test\edaboard>vlog neso_ddr3.v
    Start time: 07:42:41 on Mar 26,2020
    vlog neso_ddr3.v
    Model Technology...
  9. Replies
    7
    Views
    484

    [SOLVED]Closed: Re: Delay time calculation

    My oops, good catch.
  10. Replies
    3
    Views
    374

    [SOLVED]Closed: Re: VHDL FIFO Implementation

    Looks like the FIFO memory is really just a register file with internal read write pointers, which makes the requirement of a "When a read signal is asserted, the output of the FIFO should be...
  11. Replies
    13
    Views
    850

    Closed: Re: Error :Syntax error near "module"

    Just inspecting the posted code I don't see anything wrong with the module, specifically nothing wrong with the module declaration.

    Are you sure you compiled the posted version of code?
    Is the...
  12. Closed: Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    Not equivalent, just a similar type of function You will have to redesign, both the SERDES block implementation and the interface to the FPGA logic.

    Generally if you need to port to a new family...
  13. Closed: Re: My test pattern is not like should be! Somebody can help me please?

    I usually find tutorials by using Google. If you can't find something then a) it doesn't exist, b) you're search terms are garbage, or c) it exists but is not in Verilog.
  14. Replies
    7
    Views
    484

    [SOLVED]Closed: Re: Delay time calculation

    I don't get what your issue is exactly (which is why I ignored your first post).

    A clock has a frequency, in your case it is 50 MHz. That clock therefore has a clock period of 20 ns between each...
  15. Closed: Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    Unisim is not used to implement a design, so I'm not sure why you think unisim is causing the NgdBuild error.

    From the Virtex5 library guide ODELAYE2 is not a Virtex 5 primitive, it turns out it...
  16. Closed: Re: Problem implementing project in ISE 14.5 using ipcore fifo_generator 9.3

    That errors looks like the kind you get when you don't include the core in your design.

    As this is ISE I was expecting to see an XCI file in the directory, but there isn't one, that is normally...
  17. Replies
    6
    Views
    421

    [SOLVED]Closed: Re: 128 x 32 single port RAM VHDL code problem

    ThisIsNotSam is thinking ASIC designs not FPGA....FPGAs you can infer RAM. ASICs well that's why there are memory compilers.
  18. Closed: Re: My test pattern is not like should be! Somebody can help me please?

    more useless information, your code is wrong what implementation tools won't fix that problem.

    I think we all figured that out...so this is useless information too

    I don't even know what you...
  19. Closed: Re: My test pattern is not like should be! Somebody can help me please?

    Everything is not fine with the design, when it is not working correctly. The mistake is probably some counter is wrong.

    BTW maybe you should learn how to ask a question that can be answered.
    ...
  20. Replies
    7
    Views
    554

    [SOLVED]Closed: Re: Adding '1' to a std_logic_vector in VHDL

    adding std_logic_vectors is not supported in the numeric_std library as fourtytwo suggests use unsigned which does support arithmetic operations.



    process(clk)
    begin
    if rising_edge(clk)...
  21. Replies
    7
    Views
    1,392

    Closed: Re: Engineering in times of Covid-19

    Right, but getting anyone to clean up after themselves where I work is not likely to happen. There are people at my work that think their mommies work at the place and will clean up their mess.
  22. Replies
    7
    Views
    1,392

    Closed: Re: Engineering in times of Covid-19

    Been working remotely since last week.

    No but collaboration over a test bench are usually not required and if they are the labs we have are quire large so keeping 6ft+ distance is quite easy to...
  23. Replies
    129
    Views
    6,023

    Closed: Re: AXI arvalid signal issue

    The OP appears to have the spec, but seems to be reading it piecemeal instead of reading the whole thing through.
  24. Replies
    4
    Views
    380

    [SOLVED]Closed: Re: Using 2 push buttons to light LEDs

    I asked previously where is your testbench?

    If you want the push buttons to independently turn on/off a corresponding LED, then why do you have the code to generate score (i.e. pb_out) in the same...
  25. Replies
    129
    Views
    6,023

    Closed: Re: AXI arvalid signal issue

    The byte lanes are fixed at specific addresses so the lower order bits of the address must be consistent with the byte lane being accessed.
Results 1 to 25 of 500
Page 1 of 20 1 2 3 4